tag: system-level design

Week In Review: Design, Low Power
By Jesse Allen - 30 Nov, 2018 - Comments: 0

Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

What Makes A Good AI Accelerator
By Ann Mutschler - 25 Oct, 2018 - Comments: 3

The rapid growth and dynamic nature of AI and machine learning algorithms is sparking a rush to develop accelerators that can be optimized for different types of data. Where one general-purpose processor was considered sufficient in the past, there are now dozens vying for a slice of the market. As with any optimized system, architecting an accelerator — which is now the main processing en... » read more

What Is SOTIF?
By Ed Sperling - 10 Oct, 2018 - Comments: 0

Arteris IP’s Kurt Shuler discusses new system-level best-practices approach to automotive design that will be used for both diagnostics and forensics when something goes wrong with autonomous vehicles. https://youtu.be/nC3TkF7c0Oo » read more

Solving Systemic Complexity
By Ed Sperling - 26 Jul, 2018 - Comments: 0

EDA and IP companies have begun branching out in entirely new directions over the past 12 to 18 months, pouring resources into entirely different problems than electrostatic issues and routing complexity. While they're still focused on solving complexity at 10/7/5nm, they also recognize that enabling Moore's Law isn't the only opportunity. For an increasing number of new and established chip... » read more

The Week In Review: Design
By Jesse Allen - 15 Jun, 2018 - Comments: 0

M&A MIPS has reportedly been acquired again, this time by AI startup Wave Computing. Wave focuses on data center-based neural network training using its parallel dataflow processing architecture. In March, the company signed on to use 64-bit multi-threaded processor cores from MIPS in future projects. Previously, MIPS was owned by Tallwood Venture Capital, which acquired MIPS from Imaginat... » read more

The Week In Review: Design
By Jesse Allen - 08 Jun, 2018 - Comments: 0

Tools & IP Synopsys added machine learning capabilities to its Design Platform. The company highlighted benefits to the PrimeTime signoff tool, which saw 5X faster power recovery in customer designs at leading-edge geometries. Renesas is using the tool, noting a 4X power ECO speed-up. ArterisIP unveiled a standalone last level cache (LLC) for high-performance SoCs. CodaCache can be adde... » read more

Preparing For Bigger Changes Ahead
By Ed Sperling - 21 Dec, 2017 - Comments: 0

The semiconductor industry has undergone a fundamental shift over the past year, and it's one that will redefine chipmaking over the next decade or more. While the focus is still on building the fastest, lowest-power devices, whether that's by shrinking features or packaging them into blazing-fast 2.5D or fan-out configurations, these devices are being customized for specific use cases much ... » read more

Dealing With System-Level Power
By Ann Mutschler - 17 Jul, 2017 - Comments: 1

Analyzing and managing power at the system level is becoming more difficult and more important—and slow to catch on. There are several reasons for this. First, design automation tools have lagged behind an understanding of what needs to be done. Second, modeling languages and standards are still in flux, and what exists today is considered inadequate. And third, while system-level power ha... » read more

Performance To The People
By Ed Sperling - 13 Jul, 2017 - Comments: 0

Ever since the IoT became a household term, the almost universal concept was that extremely low-power, simplistic devices would rule the edge. They would collect data, send it to the cloud, and the cloud would send back useful information. That's a great marketing concept for gateways and cloud services, but it's not scalable. Consumers don't just want to know when their heartbeat is irregul... » read more

Toward Better Accelerators
By Kurt Shuler - 03 Jul, 2017 - Comments: 0

In the not-too-distant past, the standard mobile application processor architecture was the predominant one used for most System-on-Chip (SoC) designs, but that is rapidly changing as new systems and applications emerge in the post-mobile computing era. New requirements for autonomous driving are motivating technology innovations: Visual processing, deep neural networks and machine learning pla... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy