Week In Review: Design, Low Power

Functional safety IP; floating-point verification; AWS on Arm.


Tools & IP
UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and voting with any number of cores or subsystems. It works with any processor architecture or other subsystem, including custom logic or accelerators.

OneSpin Solutions launched a new app for formal verification of floating-point hardware compliant with the IEEE 754 standard. The Floating Point Unit App, an add-on to the company’s 360 DV Property Checker, verifies that results of arithmetic operations accurately match the standard’s specifications, checking all rounding modes and exception flags. Half, single or double precision formats can be selected, less common precisions can be accommodated, and users can selectively disable checks. All major operations are supported except division.

Allegro DVT released new video encoder IP with smart encoding features. The AL-E200 encoder IP uses an enhanced single-core hardware architecture that enables encoding of UHD/4K resolutions and provides support for multiple video codec formats by sharing resources between H.264/AVC, H.265/HEVC, VP9 and JPEG compression standards to minimize power consumption and silicon area.

IAR Systems added support for the Arm Cortex-A5 CPU to its IAR Embedded Workbench. Additionally, the embedded development toolchain’s C/C++ compiler and debugger are now available to users of Arm’s DesignStart program. IAR is also working with Andes on a toolchain for the company’s RISC-V-based cores.

AWS is now running application workloads on Arm-based Graviton processors. Designed by AWS subsidiary Annapurna Labs and based on Arm’s Neoverse “Cosmos” platform, Graviton processors will power all new Amazon EC2 A1 instances and are being targeted for scale-out workloads, including containerized microservices, web servers, development environments, and caching fleets.

MicroBT utilized Moortec’s 16FFC Temperature Sensor IP in its latest high performance computing ASIC. “Accurate temperature monitoring and management can enable products to deal with all kinds of challenges in extreme environments,” said MicroBT R&D head Guo Haifeng.

The Linux Foundation is backing the RISC-V Foundation with a joint collaboration agreement aimed at accelerating open source development and adoption of the RISC-V ISA. The Linux Foundation will provide resources such as training programs, infrastructure tools, community outreach, marketing and legal expertise.

Training companies Hardent and Willamette HDL are offering a new Portable Test and Stimulus Standard training course. The course targets Breker Verification Systems Trek5 tool suite users and will cover unique UVM/SoC deployment and modeling capabilities. The PSS standard defines a way to capture the test intent from simulation to post-silicon.

AI hardware startup Wave Computing closed its Series E funding round at $86 million, bringing total investment in Wave to over $200 million. The round was led by Oakmont Corporation; funds will be used to support worldwide growth and evolution of the company’s structure.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.

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