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Week In Review: Design, Low Power


EnSilica listed on the London Stock Exchange's AIM market under the ticker ENSI. EnSilica designs mixed signal ASICs for system developers in the automotive, industrial, healthcare, and communications markets. It also has a portfolio of core IP covering cryptography, radar and communications systems. AIM is the LSE’s market for small and medium sized growth companies. "In connection with Admi... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Cadence is now an official technology partner of the McLaren Formula 1 Team. The team will use Cadence’s Fidelity CFD Software to look at the computational fluid dynamics (CFD) of the airflow around the race cars and predict how a car design will affect the airflow. Infineon uncorked its XENSIV 60 GHz automotive radar sensor for in-cabin monitoring systems. One use ca... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive, mobility Stellantis is buying Share Now, a car sharing service owned by BMW and Mercedes-Benz. Through the acquisition, Stellantis will be adding 3.4 million car sharing customers, 10,000 vehicles, and 14 new European cities to its Free2move car sharing service, which currently has 2 million users, 2,500 vehicles, and has 7 “mobility hubs” in the U.S. and Europe. ShareNow was a... » read more

Week In Review: Design, Low Power


Rambus will acquire Hardent, a provider of design services and IP. Rambus said Hardent's silicon design, verification, compression, and Error Correction Code (ECC) expertise will provide key resources for the Rambus CXL Memory Interconnect Initiative. “Driven by the demands of advanced workloads like AI/ML and the move to disaggregated data center architectures, industry momentum for CXL-base... » read more

Rambus To Buy Hardent


Rambus inked a deal to buy Hardent, an engineering services company, in order to accelerate Rambus' push into the CXL arena. Compute Express Link (CXL), developed primarily by Intel before being turned into an open industry standard, allows memory to be disaggregated within a data center and shared across multiple servers. This, in turn, lets data centers control how critical resources are a... » read more

Week In Review: Design, Low Power


Kalray, a provider of programmable data processing and storage acceleration cards for data centers, will acquire Arcapix Holdings, which provides software-defined storage and data management solutions for data-intensive applications. "I am delighted at the prospect of this acquisition that will accelerate our go-to-market and strengthen our key position in the data-intensive storage market. It ... » read more

Auto Displays: Bigger, Brighter, More Numerous


Displays are rapidly becoming more critical to the central brains in automobiles, accelerating the adoption and evolution of this technology to handle multiple types of audio, visual, and other data traffic coming into and flowing throughout the vehicle. These changes are having a broad impact on the entire design-through-manufacturing flow for display chip architectures. In the past, these ... » read more

New Power, Performance Options At The Edge


Increasing compute intelligence at the edge is forcing chip architects to rethink how computing gets partitioned and prioritized, and what kinds of processing elements and memory configurations work best for a particular application. Sending raw data to the cloud for processing is both time- and resource-intensive, and it's often unnecessary because most of the data collected by a growing nu... » read more

Shifting Toward Data-Driven Chip Architectures


An explosion in data is forcing chipmakers to rethink where to process data, which are the best types of processors and memories for different types of data, and how to structure, partition and prioritize the movement of raw and processed data. New chips from systems companies such as Google, Facebook, Alibaba, and IBM all incorporate this approach. So do those developed by vendors like Appl... » read more

Week In Review: Design, Low Power


Tools & IP Codasip unveiled three commercially licensed add-ons to the Western Digital SweRV Core EH1, aiming to allow it to be designed into a wider range of applications. The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. The add-ons offer a floating-point unit (FPU) that supports the RISC-V single precision [F] and d... » read more

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