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Week In Review: Design, Low Power


Tools & IP Codasip unveiled three commercially licensed add-ons to the Western Digital SweRV Core EH1, aiming to allow it to be designed into a wider range of applications. The SweRV Core EH1 is a 32-bit, dual-issue, RISC-V ISA core with a 9-stage pipeline, open-sourced through CHIPS Alliance. The add-ons offer a floating-point unit (FPU) that supports the RISC-V single precision [F] and d... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive/Mobility General Motors is working on a next version of Ultium battery chemistry and announced a joint development agreement with Singapore-based SolidEnergy Systems, a lithium metal battery startup founded by a graduate of MIT. The companies plan to open a Woburn, Massachusetts prototype production line by 2023. GM’s is attempting to lower the cost of its proprietary battery tech... » read more

Week In Review: Design, Low Power


Tools, Cloud, IP Valtrix Systems updated its STING design verification tool for RISC-V based CPU and SoC implementations. Version 1.9.0 adds support to verify recent changes to the RISC-V user and privilege specifications, including draft versions of the vector and bit manipulation standard extensions. Preliminary support for the draft version of the RISC-V hypervisor extension has also been a... » read more

Week In Review: Auto, Security, Pervasive Computing


Automotive Austin, Texas-based automotive startup Uhnder raised $45 million in Series C funding for its digital radar-on-chip. Telechips, a fabless semiconductor company that works on automotive SoCs, is using Arm’s IP to design its Dolphin5 SoC for ADAS (advanced drive assistance systems) and digital cockpits with in-vehicle infotainment (IVI). Dolphin5 will include the Arm’s Mali-G78A... » read more

Week In Review: Design, Low Power


Tools & IP UltraSoC debuted functional safety-focused Lockstep Monitor, a set of configurable IP blocks that are protocol aware and can be used to cross-check outputs, bus transactions, code execution, and register states between two or more redundant systems. It supports all common lockstep / redundancy architectures, including full dual-redundant lockstep, split/lock, master/checker, and... » read more

The Week In Review: Design


Tools & IP Synopsys uncorked ASIL B, C, and D ready versions of its DesignWare EV6x Embedded Vision Processors for automotive SoCs. An included Safety Enhancement Package provides hardware safety features, safety monitors, and lockstep capabilities for safety-critical designs. The processors integrate scalar, vector DSP, and CNN processing units for automotive systems that require deep lea... » read more

The Week In Review: Design


M&A PLDA is divesting its Reflex CES brand. The FPGA board maker will become wholly managed by its own management and investment teams. In 2015, Reflex CES took over the hardware businesses of PLDA, including FPGA-based boards and the System-on-Module product lines. Tools Mentor uncorked a new tool for in-system test and diagnosis of automotive ICs. Tessent MissionMode provides infrast... » read more

The Week In Review: Design/IoT


Mergers & Acquisitions NXP added to its list of recent acquisitions with Athena SCS, a UK-based provider of embedded software and cryptography for smart cards and NFC. Lattice Semiconductor closed its all-cash $606.6 million acquisition of Silicon Image. Tools Cadence unveiled the Innovus Implementation System. The physical implementation tool sports massively parallel architect... » read more