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Week In Review: Design, Low Power

Kalray acquires software-defined storage; PCIe 6.0 controller; HBM3 standard; Xilinx record results.

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Kalray, a provider of programmable data processing and storage acceleration cards for data centers, will acquire Arcapix Holdings, which provides software-defined storage and data management solutions for data-intensive applications. “I am delighted at the prospect of this acquisition that will accelerate our go-to-market and strengthen our key position in the data-intensive storage market. It is perfectly aligned with Kalray’s development strategy and ambition, complimenting our products, team, expertise and markets. With this acquisition, we would gain new clients and strategic partners to propel our business forward,” said Eric Baissus, president and CEO of Kalray. The cash and stock deal is worth approximately €17.7M (~$20.1M).

Tools
Thalia Design Automation updated the Technology Analyzer and Circuit Porting tools in its IP reuse and development platform. It adds machine learning to analyze waveforms and propose candidate solutions, as well as the ability to extract the noise, DC, and AC characteristics over corners and Monte Carlo analysis. “Particularly now, when capacity at wafer fabs is tight, it’s important that designers remain agile to access chip manufacturing where it’s available, and where it is cost effective,” said Thalia CEO Sowmyan Rajagopalan. It now supports a range of process technologies from 350nm down to 22nm including FDSOI.

Pearl Semiconductor adopted Siemens Digital Industries Software’s Symphony Mixed-Signal Platform for developing and verifying its newest ultra-low noise digital phased locked loop (PLL) design, which targets a range of demanding applications such as high-speed connectivity, high bandwidth video broadcasting and 5G infrastructure markets. “Our novel PLL architecture continuously suppresses spurs, while minimizing the noise contribution of active circuitry within the PLL bandwidth,” said Mohamed Dessouky, vice president of engineering for Pearl Semiconductor. “The flexibility of Symphony to work with our mixed-signal use cases and the tool’s ease-of-use resulted in wider adoption across our verification teams and resulted in 4X productivity improvement.”

Wistron Corporation adopted Ansys simulation software to automate power density analysis of its 5G cell phone antenna and optimize signal coverage. Wistron Corporation used the simulation solutions to optimize antenna performance with HFSS-encrypted modules provided by module manufacturers by tuning the location and orientation of the modules to achieve the correct power density and optimize the signal coverage needed for FCC-compliant performance. “Replacing our traditional measurement tools with simulation helps us to produce 5G phones with greater efficiency and reinforces customers’ competitive advantages in the market,” said Howard Liu, vice president of vertical business group at Wistron.

IP
Rambus announced its PCIe 6.0 Controller. The controller provides data rates up to 64 GT/s for high-performance applications. In addition, the controller provides an Integrity and Data Encryption (IDE) security engine that monitors and protects PCIe links against physical attacks. “The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power and area,” said Sean Fan, chief operating officer at Rambus. “As the latest addition to our portfolio of industry-leading interface IP, our PCIe 6.0 Controller offers customers an easy to integrate solution that delivers both performance and security for advanced SoCs and FPGAs.”

CEVA introduced an IP solution that aims to enable secure data exchange between different chiplets within a heterogenous SoC. Fortrix SecureD2D IP offers secure authentication and firmware boot/code load between chiplets and consists of a controller communicating over a secure fabric to hardware-based crypto accelerators which perform rapid encryption and decryption to enable cryptographic functions such as ECDSA, SHA2, AES, and others. “We’re pleased to make this IP available within the DoD SHIP program and we look forward to helping secure the next-generation of HSoC devices,” said Mark Beal, CTO of the Intrinsix Business Unit at CEVA. A low-level firmware API and a customizable high-level application are also part of the IP package.

Hardent uncorked a new VESA Display Stream Compression (DSC) Frame Buffer Compression IP subsystem. Designed for Timing Controller (TCON) ICs with Embedded DisplayPort (eDP) interfaces, the IP subsystem aims to reduce frame buffer area when using the new eDP 1.5 low power mode.

FPGA
Xilinx reported third quarter 2022 financial results with revenue of $1,011 million, up 26% compared to the same quarter last year. “Record Q3 revenue was driven primarily from sequential growth in A&D [Aerospace & Defense], DCG [Data Center Group] and TME [Test, Measurement & Emulation], leading to total sequential revenue growth of 8% and year-over-year growth of 26%, the fifth consecutive quarter of double-digit year-over-year growth,” said Brice Hill, Xilinx CFO. “Overall strong revenues and business mix, in addition to positive impacts from strategic venture investments, drove record earnings this quarter. Our platform strategy continues to progress as Adaptive SoC revenue grew 5% sequentially and 30% year-over-year, representing 28% of total revenue.” Hill also noted that a stated increase in inventory to 106 days was primarily driven by supply cost increases, not a significant increase in unit inventory.

Memory
JEDEC published the latest version of the High Bandwidth Memory DRAM standard, HBM3. Key to the new standard is a doubling of the per-pin data rate of HBM2 generation and defining data rates of up to 6.4 Gb/s, equivalent to 819 GB/s per device; doubling the number of independent channels to 16; supporting 4-high, 8-high, and 12-high TSV stacks with provision for a future extension to a 16-high TSV stack; support for a wide range of densities; symbol-based ECC on-die and real-time error reporting and transparency for increased reliability; and improved energy efficiency by using low-swing (0.4V) signaling on the host interface and a lower (1.1V) operating voltage.

Weebit Nano, partnering with CEA-Leti, demonstrated its first operational crossbar arrays that combine its ReRAM technology with a selector. Weebit said it developed it crossbar arrays using a 1S1R (one selector one resistor) architecture that enables the high density needed for discrete chips and allows the arrays to be stacked in 3D layers. Potential applications include storage class memory, persistent memory and as a NOR flash replacement. “With the creation of our first kilobit crossbar arrays, which combine our ReRAM technology with CEA-Leti’s selector technology, we’re continuing our progress toward discrete memory solutions,” said Weebit CEO Coby Hanoch. “Developing such a crossbar array is a very innovative process that requires significant research. As part of this work, we recently filed several new patents together with CEA-Leti, designed to further protect Weebit’s ReRAM intellectual property, with a focus on 1S1R architectures and selector cell programming.”

Industrial
Infineon uncorked a complete system solution for motor control. The pre-assembled kit includes a chipset combined with pre-flashed sample software as well as a BLDC motor. Applications include auxiliary pumps, cooling fans, HVAC blowers, or any other application that uses 3-phase low voltage BLDC motors.

Lockheed Martin’s Aeronautics business selected Siemens’ Xcelerator portfolio to support its digital engineering efforts. “Building off of our experience on the F-35 program, and through close collaboration, Siemens is excited to help Lockheed Martin accelerate production and meet DoD contract requirements for both current programs and new initiatives,” said Tony Hemmelgarn, President and Chief Executive Officer, Siemens Digital Industries Software.



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