A Design Flow For Critical Embedded Systems

By Arteris - 23 Aug, 2023 - Comments: 0

Learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems. Includes usage of these capabilities integrated using Arteris SoC integration technology: HW/SW codesign RTL, SystemC TLM and PSL Instruction Set Simulators Click here to read more. » read more

RISC-V: Advanced Virtual Prototyping Solutions

By Technical Paper Link - 23 May, 2022 - Comments: 0

New technical paper titled "Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges" from researchers at Institute of Computer Science, University of Bremen and Cyber-Physical Systems, DFKI GmbH. Abstract "Virtual prototypes (VPs) are crucial in today’s design flow. VPs are predominantly created in SystemC transaction-level modelin... » read more

DAC 2018: System Design, Cloud And Machine Learning

By Frank Schirrmeister - 28 Jun, 2018 - Comments: 0

This marks the 10th DAC that I have covered as a blogger. At DAC 2008 in Anaheim, the industry had just come together behind the SystemC TLM 2.0 standard to enable virtual platforms, finally getting to model interoperability. System design is the common thread that is also present in this year’s DAC in 2018 in San Francisco. But a lot has changed. Big data analytics, artificial intelligence a... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: SystemC TLM

A Design Flow For Critical Embedded Systems

RISC-V: Advanced Virtual Prototyping Solutions

DAC 2018: System Design, Cloud And Machine Learning