Fast Models, Cycle Models


There has been a lot of coverage since the launch of new CPU and graphics cores at Computex 2017, including some information about early software development. The public announcement of new ARM IP is a milestone for ARM Models because it means we can now talk about available models and share additional information about the new IP. ARM Fast Models and Cycle Models enable virtual prototyping ... » read more

Hybrid Emulation


Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Formal Verification’s Continental Divide


Formal verification is picking up steam with engineering groups worldwide doing complex functional verification for bug-free and reliable digital chips. In fact, many difficult verification challenges are solved with formal verification, given its flexibility in targeting a broad range of verification challenges. Recent advances in formal verification’s ease of use and capacity has made it an... » read more

Whatever Happened To HLS?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high-lev... » read more

Whatever Happened to High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Whatever Happened To High-Level Synthesis?


A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology. It was to be the heart of a new Electronic System Level (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high level design and verificati... » read more

Hybrid Simulation Picks Up Steam


As electronic products shift from hardware-centric to software-directed, design teams are relying increasingly on a simulation approach that includes multiple engines—and different ways to use those engines—to encompass as much of the system as possible. How engineers go about using these approaches, and even how they define them, varies greatly from one company to the next. Sometimes it... » read more

Using High-Level Synthesis To Design And Verify 802.11ah Baseband IP


The proposed IEEE 802.11ah wireless networking protocol is designed to meet the requirements of Internet of Things (IoT) connectivity, providing the bit rate, security, and low power required for these types of connected devices. Design requirements for 802.11ah access point and clients vary widely, even though all implement the same mathematical algorithm. In this paper, we will discuss how... » read more

Tech Talk: Earlier Software


Malte Doerper, senior manager of product management at Synopsys, talks about the big "shift left" for software, where the problems crop up, and how to save as much as a year of development time with automation and better methodologies.   Related Stories Bridging Hardware And Software The need for concurrent hardware-software design and verification is increasing, but are engine... » read more

Gaps In The Verification Flow


Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

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