Next EUV Issue: Mask 3D Effects


As extreme ultraviolet (EUV) lithography moves closer to production, the industry is paying more attention to a problematic phenomenon called mask 3D effects. Mask 3D effects involve the photomask for EUV. In simple terms, a chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for a given IC design. It is placed in a lithography scan... » read more

Politics And (Low) Power


This week the entire semiconductor market woke up with a severe political hangover. Aside from the initial shock of the election results themselves, the winning platform of "America First" could have far-reaching implications for an industry that has spent decades optimizing a global supply chain the way it has finely tuned other processes to reduce the cost per transistor. There are many un... » read more

Trade War Looms Over Materials


It’s time to pay close attention to rare earths and raw materials--again. In fact, the supply chain teams and commodity buyers at aerospace, automotive and electronics companies may have some new and potentially big problems on their hands. For some time, the European Union (EU), the United States and other nations have been at odds with China over rare earths. China, which accounts for... » read more

Power/Performance Bits: Aug. 18


Reducing crosstalk with tantalum oxide memories Scientists at Rice University created a solid-state memory technology that allows for high-density storage with a minimum incidence of crosstalk errors. The memories are based on tantalum oxide. Applying voltage to a 250-nanometer-thick sandwich of graphene, tantalum, nanoporous tantalum oxide and platinum creates addressable bits where the ... » read more

It’s a Materials World, With Positive Forecast


By Michael Fury What’s the latest in materials forecasts for ALD/CVD precursors, CMP consumables, electronic gases, silicon wafers and sputtering targets? Techcet gives us an update. Metal Gate and Electrode Precursors to Double in Five Years Use of front-end Ta and W metal gate and Hf gate dielectric precursors will grow over 2.5x by 2020, according to a new report from Techcet, “20... » read more

EU Due Diligence For Conflict Minerals Focuses Upstream, For Now


By Rania Georgoutsakou EU proposed legislation on responsible sourcing of ‘conflict minerals’, published on 5 March 2014, will create a voluntary scheme focusing on upstream suppliers that should help downstream users get the information they need to comply with the U.S. Dodd Frank Act. The EU proposals largely address concerns raised by SEMI and other industry associations, but things cou... » read more

Interconnect Challenges Grow


Qualcomm outlined the technology challenges facing mobile chip suppliers at a recent event. In no particular order, the challenges include the usual suspects—area scaling, power reduction, performance and cost. Another concern for Qualcomm is an often-overlooked part of the equation—the backend-of-the-line (BEOL). In chip production, the BEOL is where the interconnects are formed within ... » read more

Power/Performance Bits: Nov. 26


Many people are predicting that power will be the issue that brings Moore’s Law to an end. Power creates heat and that heat can be destructive to chips, so there are two paths forward – the first is to reduce heat and the second is to get it off chip. It seems as if magnets may be the common key to both approaches. Magnetic Transistors New work by researchers at UC Berkeley soon could t... » read more

The Search For New Materials


It makes sense that the first chips were built out of silicon. It’s hard to think of a more abundant material than sand, or one that’s so easily accessible in so many places. It’s like building the first homes out of earthen bricks. There was never a shortage of materials. Even aluminum and copper for the wires and interconnects in these chips are readily available, despite the rising ... » read more

Challenges Mount For Interconnect


By Mark LaPedus There are a plethora of chip-manufacturing challenges for the 20nm node and beyond. When asked what are the top challenges facing leading-edge chip makers today, Gary Patton, vice president of the Semiconductor Research and Development Center at IBM, said it boils down to two major hurdles: lithography and the interconnect. The problems with lithography are well documented.... » read more