Formal Verification Methodology For Detecting Security-Critical Bugs in HW & in the HW/Firmware Interface of SoCs (Award Winner)

A new technical paper titled "A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level" was this year's first place winner of Intel's Hardware Security Academic Award program.   The approach utilizes UPEC (Unique Program Execution Checking) to identify functional design bugs causing confidentiality violations, covering both the processor and its peripherals. ... » read more

OneSpin Users Gather in Munich

Even more than most other high-tech companies, EDA vendors rely on their users for many aspects of their success. Of course, customers provide the revenue that fuels the business, but their influence goes far beyond that. Many features in EDA tools, and even entire categories of products, arise from working closely with advanced users. Even before traditional Beta-testing, selected users provid... » read more

System Bits: April 18

RISC-V errors Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retr... » read more