AI Feeds Vision Processor, Image Sensor Boom


Vision systems are rapidly becoming ubiquitous, driven by big improvements in image sensors as well as new types of sensors. While the sensor itself often is developed using mature-node silicon, increasingly it is connected to vision processors developed at the most advanced process nodes. That allows for the highest performance per watt, and it also allows designs to incorporate AI accelera... » read more

Week In Review: Semiconductor Manufacturing, Test


Fallout from the new U.S. export controls continues. Under new regulations, companies looking to supply Chinese chipmakers with advanced manufacturing equipment (<14nm) must first obtain a license from the U.S. Department of Commerce. In addition, U.S. persons (citizens and permanent residents) are barred from supporting China’s advanced chip development or production without a license. ... » read more

Wafer Cleaning Becomes Key Challenge In Manufacturing 3D Structures


Wafer cleaning, once a rather mundane task as simple as dipping wafers in cleaning fluid, is emerging as one of the top major engineering challenges for manufacturing GAA FETs and 3D-ICs. With these new 3D structures — some on the horizon but some already in high-volume manufacturing — semiconductor wafer equipment and materials suppliers in the wet cleaning business are at the epicenter... » read more

What’s Different About Next-Gen Transistors


After nearly a decade and five major nodes, along with a slew of half-nodes, the semiconductor manufacturing industry will begin transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures at the 3nm technology node. Relative to finFETs, nanosheet transistors deliver more drive current by increasing channel widths in the same circuit footprint. The gate-all-aroun... » read more

Metal Oxide Resist (MOR) EUV Lithography Processes For DRAM Application


This paper reports the readiness of key EUV resist process technologies using Metal Oxide Resist (MOR) aiming for the DRAM application. For MOR, metal contamination reduction and CD uniformity (CDU) are the key performance requirements expected concerning post exposure bake (PEB). Based on years of experience with spin-on type Inpria MOR, we have designed a new PEB oven to achieve contamination... » read more

Week In Review: Manufacturing, Test


President Biden signed an executive order on Sept. 15, limiting foreign investments in U.S. technology by "competitor or adversarial nations" that are deemed a threat to national security. In the past, the Committee on Foreign Investment in the United States (CFIUS) largely limited its actions to the sale of U.S. companies. The new directive expands that to include investments involving "U.S. s... » read more

Smart Manufacturing And Advanced Technical Service


SEMI spoke with Eyal Shekel, senior vice president of Service Strategy and Excellence at Tokyo Electron Limited, about the impact of artificial intelligence (AI) on smart manufacturing and how other fab solutions for smarter process tools are advancing semiconductor manufacturing. SEMI: AI technology is considered a key enabler for smart manufacturing. What are the latest trends? Shekel:... » read more

Week In Review: Manufacturing, Test


Some funding details are now available for the CHIPS Act in the U.S. The Biden Administration plans to spend the money in the following ways: $28 billion to establish domestic production of leading-edge logic and memory chips through grants, subsidized loans or loan guarantees; $10 billion to increase production of current-generation semiconductors and chips, and $11 billion for rese... » read more

Week In Review: Manufacturing, Test


Government funding President Biden signed the CHIPS and Science Act into law on Tuesday, saying “America is back and leading the way.” That same day Micron touted a $40 billion investment through to 2030, which it expects will create 40,000 American jobs. “This legislation will enable Micron to grow domestic production of memory from less than 2% to up to 10% of the global market in t... » read more

Hybrid Bonding Moves Into The Fast Lane


The industry’s unquenchable thirst for I/O density and faster connections between chips, particularly logic and cache memory, is transforming system designs to include 3D architectures, and hybrid bonding has become an essential component in that equation. Hybrid bonding involves die-to-wafer or wafer-to-wafer connection of copper pads that carry power and signals and the surrounding diele... » read more

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