Pinpointing Timing Delays in Complex SoCs


Telemetry circuits are becoming a necessity in complex heterogeneous chips and packages to show how these devices are behaving post-production, but fusing together relevant data to identify the sources of problems adds its own set of challenges. In the past, engineering teams could build margin into chips to offset any type of variation. But at advanced nodes and in advanced packages, tolera... » read more

Week In Review: Semiconductor Manufacturing, Test


China retaliated against a U.S. embargo on advanced semiconductor equipment exports by restricting exports of gallium and germanium. Both metals are widely used in semiconductors and electric vehicles. Despite export controls for advanced chips and equipment imposed on Chinese foundries by the U.S. and its allies, TrendForce predicts China's 300mm market share likely will increase from 24% ... » read more

Journey From Cell-Aware To Device-Aware Testing Begins


Early results of using device-aware testing on alternative memories show expanded test coverage, but this is just the start. Once the semiconductor industry realized that it was suffering from device failures even when test programs achieved 100% fault coverage, it went about addressing this disconnect between the way defects manifest themselves inside devices and the commonly used fault mod... » read more

Ramping Up Power Electronics For EVs


The rapid acceleration of the power devices used in electric vehicles (EVs) is challenging chipmakers to adequately screen the ICs that power these vehicles.[1] While progress toward autonomous driving is grabbing the public’s attention, the electrification of transportation systems is progressing quietly. For the automotive industry, this shift involves a mix of electronic components. Amo... » read more

Testing High Power Discrete Devices


Emerging markets are driving the evolution of discrete power devices. Increased power requirements mean more power is being driven through a smaller device, creating challenges in both device design and test. This video series, 3 for 3, provides 3 answers for 3 pressing questions about trends in semiconductor test, and how testing for high power discrete devices is evolving. » read more

Chiplet Planning Kicks Into High Gear


Chiplets are beginning to impact chip design, even though they are not yet mainstream and no commercial marketplace exists for this kind of hardened IP. There are ongoing discussions about silicon lifecycle management, the best way to characterize and connect these devices, and how to deal with such issues as uneven aging and thermal mismatch. In addition, a big effort is underway to improve... » read more

Pinpointing Timing Delays Can Improve Chip Reliability


Growing pressure to improve IC reliability in safety- and mission-critical applications is fueling demand for custom automated test pattern generation (ATPG) to detect small timing delays, and for chip telemetry circuits that can assess timing margin over a chip's lifetime. Knowing the timing margin in signal paths has become an essential component in that reliability. Timing relationships a... » read more

Optimizing Scan Test For Complex ICs


As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin availability. In addition, the complexity of emerging packages like 3D and chiplets necessitates comprehensive new solutions that can provide faster results at multiple stages in the silicon lifec... » read more

What Data Center Chipmakers Can Learn From Automotive


Automotive OEMs are demanding their semiconductor suppliers achieve a nearly unmeasurable target of 10 defective parts per billion (DPPB). Whether this is realistic remains to be seen, but systems companies are looking to emulate that level of quality for their data center SoCs. Building to that quality level is more expensive up front, although ultimately it can save costs versus having to ... » read more

Image Sensors Are Everywhere And The Implications For Test Are Significant


In February of 2021, the NASA Perseverance rover actively navigated a fully-autonomous entry and descent to successfully land in the Jezero Crater on Mars, using a brand-new navigational system developed by NASA – Terrain-Relative Navigation. The delay between mission control and the rover was about 11 minutes so a human-guided remote landing was not possible. Previous missions had to rely o... » read more

← Older posts Newer posts →