From Mobile Phones To Robotics: How The Industry Continues To Drive Innovation


I recently had the opportunity to host Pierre Cambou, Principal Analyst for Global Semiconductors at Yole Group, on the Advantest podcast. What struck me about our conversation was while we focused on what was going on in the mobile market, the entire talk was reflective of the cyclical nature of the semiconductor industry and how technology can drive intense cycles of innovation. As Pierre ... » read more

Challenges And Outlook Of ATE Testing For 2nm SoCs


The transition to the 2nm technology node introduces unprecedented challenges in Automated Test Equipment (ATE) bring-up and manufacturability. As semiconductor devices scale down, the complexity of testing and ensuring manufacturability increases exponentially. 3nm silicon is a mastered art now, with yields hitting pretty high for even complex packaged silicon, while the transition from 3nm to... » read more

Ensuring Multi-Die Package Quality And Reliability


Multi-die designs are gaining broader adoption in a wide variety of end applications, including high-performance computing, artificial intelligence (AI), automotive, and mobile. Despite clear advantages, there are new challenges that need to be addressed for successful multi-die realization. This article gives a high-level overview of the multi-die test challenges that go beyond the design p... » read more

Bluetooth’s New Era: The Role Of Channel Sounding And Adaptable Testing Solutions


By Jake Harnack and Alejandro Escobar Calderon Bluetooth technology has experienced a remarkable transformation since its inception, evolving from a basic tool for data transfer to a near-ubiquitous wireless technology used for audio streaming, location services, and smart-home networks. As sales of Bluetooth-enabled devices nears 5 billion units per year in 2024, the Bluetooth standard is e... » read more

Are You Ready For HBM4? A Silicon Lifecycle Management (SLM) Perspective


Many factors are driving system-on-chip (SoC) developers to adopt multi-die technology, in which multiple dies are stacked in a three-dimensional (3D) configuration. Multi-die systems may make power and thermal issues more complex, and they have required major innovations in electronic design automation (EDA) implementation and test tools. These challenges are more than offset by the advantages... » read more

Semiconductor Shifts In Automotive: Impact Of EV And ADAS Trends


The integration of advanced driver assistance systems (ADAS) and the transition towards electric vehicles (EVs) are significantly transforming the automotive industry. Modern vehicles, essentially computers on wheels, require substantially more semiconductors. In response, carmakers are forming stronger partnerships with semiconductor vendors – some are taking a page from tech giants like ... » read more

Driving Cost Lower and Power Higher With GaN


Gallium nitride is starting to make broader inroads in the lower-end of the high-voltage, wide-bandgap power FET market, where silicon carbide has been the technology of choice. This shift is driven by lower costs and processes that are more compatible with bulk silicon. Efficiency, power density (size), and cost are the three major concerns in power electronics, and GaN can meet all three c... » read more

Leveraging AI To Efficiently Test AI Chips


In the fast-paced world of technology, where innovation and efficiency are paramount, integrating artificial intelligence (AI) and machine learning (ML) into the semiconductor testing ecosystem has become of critical importance due to ongoing challenges with accuracy and reliability. AI and ML algorithms are used to identify patterns and anomalies that might not be discovered by human testers o... » read more

The Semiconductor Revolution And The Role Of Adaptable Testing


The semiconductor industry, the backbone of modern technology, is experiencing a rapid evolution driven by the increasing demands for higher performance, greater functionality, and lower power consumption. This evolution is creating new challenges and opportunities in the testing of mixed signal and RF semiconductors and electronics devices, making the need for adaptable and flexible test syste... » read more

Reducing Design Margins With Silicon Model Calibration


By Guy Cortez and Mark Laird It’s no secret to anyone that chip design gets harder every year. There are two major trends driving these ever-increasing challenges. The first is the continual scaling down to smaller design nodes. Although the pace of new node introduction has slowed somewhat in recent years, the impact of each new geometry and process is more dramatic than ever before. Acce... » read more

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