tag: test

Reliability At 5nm And Below
By Ed Sperling - 10 Dec, 2019 - Comments: 2

The best way to figure out how a chip or package will age is to bake it in an oven, heat it in a pressure cooker, and stick it in a freezer. Those are all standard methods to accelerate physical effects and the effects of aging, but it's not clear they will continue working as chips shrink to 5nm and 3nm, or as they are included in multi-die packages. Extending any of those kitchen-like appr... » read more

Gaps Emerge In Test And Analytics
By Ed Sperling - 10 Dec, 2019 - Comments: 0

Sensor and process drift, increased design complexity, and continued optimization of circuitry throughout its lifetime are driving test and analytics in new directions, requiring a series of base comparisons against which equipment and processes can be measured. In the design world this type of platform is called a digital twin, but in the test world there is no equivalent today. And as more... » read more

Squeezing Out More Test Compression
By Jeff Mayer - 10 Dec, 2019 - Comments: 0

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been quite effective at containing test costs. For many designs, standard test compressions is enough, but ICs for use in automotive and medical devices require a higher manufacturing test quality, which t... » read more

Improving Test Pattern Compression With Tessent VersaPoint Test Point Technology
By Mentor, a Siemens Business - 09 Dec, 2019 - Comments: 0

Mission-critical applications within markets such as transportation and medical devices require higher overall manufacturing test quality, but that often means more test patterns, data volume, and longer test times. Embedded test compression helps, but using VersaPoint test point technology results in 46X compression ration over what is possible with Tessent TestKompress alone. To read more,... » read more

Six Things You Need To Know About USB Instrument Control
By NI - 09 Dec, 2019 - Comments: 0

With plug-and-play connectivity and the near ubiquity of USB ports on modern PCs and laptops, USB has become a popular choice for controlling stand-alone instrumentation. As more instrument manufacturers begin to include USB ports on their devices, it is important to understand several issues surrounding USB to ensure the longevity of your test system. To read more, click here. » read more

Using Digital Twins And DL In Lithography
By Ed Sperling - 21 Nov, 2019 - Comments: 0

Leo Pang, chief product officer and executive vice president at D2S, looks at the results of inverse lithography technology at advanced nodes using curvilinear patterns, and how that can be combined with a digital twin and deep learning speed up time to market and reduce cost. » read more

AI’s Blind Spots
By Ed Sperling - 12 Nov, 2019 - Comments: 1

The rush to utilize AI/ML in nearly everything and everywhere raises some serious questions about how all of this technology will evolve, age and perform over time. AI is very useful at doing certain tasks, notably finding patterns and relationships in broad data sets that are well beyond the capabilities of the human mind. This is very valuable for adding efficiency into processes of all so... » read more

A Breakthrough In Silicon Bring-Up
By Matthew Knowles - 12 Nov, 2019 - Comments: 1

The current semiconductor market is seeing increasingly complex silicon devices for applications like 5G wireless communications, autonomous driving, and artificial intelligence. One of the ways designers are working to control design time and cost is through the adoption of IJTAG (IEEE 1687) for a plug-and-play style IP integration during design. The benefits of using IJTAG are still emerging,... » read more

Leveraging Data In Chipmaking
By Ed Sperling - 12 Nov, 2019 - Comments: 0

John Kibarian, president and CEO of PDF Solutions, sat down with Semiconductor Engineering to talk about the impact of data analytics on everything from yield and reliability to the inner structure of organizations, how the cloud and edge will work together, and where the big threats are in the future. SE: When did you recognize that data would be so critical to hardware design and manufact... » read more

How 5G Affects Test
By Ed Sperling - 11 Nov, 2019 - Comments: 0

David Hall, head of semiconductor marketing at National Instruments, talks with Semiconductor Engineering about architectural changes to infrastructure due to the rollout of 5G and how the move from macrocells to small cells is changing test requirements.         Subscribe to Semiconductor Engineering's YouTube Channel here » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy