tag: throughput

How To Choose The Right Memory
By Ann Mutschler - 02 Apr, 2018 - Comments: 0

When it comes to designing memory, there is no such thing as one size fits all. And given the long list of memory types and usage scenarios, system architects must be absolutely clear on the system requirements for their application. A first decision is whether or not to put the memory on the logic die as part of the SoC, or keep it as off-chip memory. "The tradeoff between latency and th... » read more

Why Is Semiconductor Schedule Predictability Boring?
By Kurt Shuler - 24 Mar, 2016 - Comments: 0

Why is it not sexy to talk about the manageability of system-on-chip (SoC) projects? As an IP vendor, we are constantly bombarded with questions about how our technology can enhance performance, reduce latency, and lower power consumption. At the same time, reducing cost and time to market for the SoC design conflict with these requirements, even though they rank right up there among the top en... » read more

Resist Sensitivity, Source Power, And EUV Throughput
By Katherine Derbyshire - 30 Sep, 2015 - Comments: 0

In a recent article, I quoted 15 mJ/cm2 as the target sensitivity for EUV photoresists, and discussed the throughput that could be achieved at various source power levels. However, as a commenter on that article pointed out, reaching the 15 mJ/cm² target while also meeting line roughness requirements is itself a challenging problem. Because of the high energy of EUV photons, a highly sensitive... » read more

Tech Talk: USB Type-C
By Ed Sperling - 30 Jul, 2015 - Comments: 1

NXP's Ravi Shah explains how to design in the new USB standard, what to watch out for and why it's going to be so important for mobile and connected devices. [youtube vid=iPCwpaPy1pw] » read more

The Interconnect Bottleneck
By Ann Mutschler - 28 May, 2015 - Comments: 0

With communications playing a crucial role in the design and performance of multi-core SoCs, various interconnect structures have been proposed as promising solutions to simplify and optimize SoC design. However, sometimes things don’t go as planned and the interconnect becomes the bottleneck. “Under high utilization cases the DRAM will be over-constrained with requests from all the a... » read more

How VXLAN-Based Ethernet IP Solves Cloud Computing Network Bottlenecks
By Synopsys - 10 Sep, 2014 - Comments: 0

Network virtualization technologies running over optimized Ethernet IP are enabling cloud computing data centers to expand and support the growing amount of internet traffic. Hyperscale cloud data centers are driving requirements for new network overlay protocols such as Virtual Extensible LAN (VXLAN) running over Ethernet. This whitepaper discusses in detail the benefits of VXLAN and how it ca... » read more

Are Processors Running Out Of Steam?
By Ed Sperling - 24 Feb, 2014 - Comments: 1

Check out any smart phone these days and you’ll find some reference to the number of cores in the device. It’s not the number of cores that makes a difference, though—or even the clock speed at which they run. Performance depends on the underlying design for how they’re utilized, how often that happens, how much memory they share, how much interaction there is between the cores, and the... » read more

Memory Architectures Undergo Changes
By Ed Sperling - 22 Aug, 2013 - Comments: 0

By Ed Sperling Memory architectures are taking some new twists. Fueled by multi-core and multiple processors, as well as some speed bumps using existing technology, SoC makers are beginning to rethink how to architect, model and assemble memory to improve speed, lower power and reduce cost. What’s unusual about all of this is that it doesn’t rely on new technology, although there certai... » read more

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