Scaling AI Chip Design With NoC Soft Tiling

By Andy Nightingale - 26 Nov, 2024 - Comments: 0

Tiling is about repeating modular units within the same chip to enhance scalability and efficiency; chiplets involve combining different silicon pieces to achieve a more diverse and powerful system within a single package. Network-on-chip (NoC) soft tiling is complimentary but distinct from chiplets described above as it repeats modular units inside a NoC design. Soft tiling within a NoC off... » read more

Accelerate AI SoC Designs with NoC Tiling

By Arteris - 30 Oct, 2024 - Comments: 0

Network-on-chip (NoC) tiling technology is revolutionizing AI and machine learning-enabled semiconductor designs. This emerging approach uses proven, robust network-on-chipIP to facilitate scaling, condense design time, speed testing and reduce design risk. It allowsSoC architects to create modular, scalable designs by replicating soft tiles across the chip. Each soft tile represents a self-con... » read more

Tile-based massively scalable MIMO and phased arrays for 5G/B5G-enabled smart skins and reconfigurable intelligent surfaces

By Technical Paper Link - 20 Apr, 2022 - Comments: 0

New technical paper from Georgia Tech. Abstract "This work presents a novel tile based approach to constructing, in a modular fashion, massively scalable MIMO and phased arrays for 5G/B5G millimeter-wave smart skins and large-area reconfigurable intelligent surfaces for Smart Cities and IoT applications. A proof-of-concept 29 GHz 32 elements phased array utilizing 2×2 “8-element subarr... » read more

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tag: tiling

Scaling AI Chip Design With NoC Soft Tiling

Accelerate AI SoC Designs with NoC Tiling

Tile-based massively scalable MIMO and phased arrays for 5G/B5G-enabled smart skins and reconfigurable intelligent surfaces