tag: time-to-market

Why Traceability Matters
By Ed Sperling - 02 Mar, 2022 - Comments: 0

More heterogeneous and increasingly dense chip designs make it much harder to stay on track with initial specifications. Paul Graykowski, senior technical marketing manager at Arteris IP, talks about matching requirements to the design, the impact of ECOs and other last-minute changes, and best practices for managing revisions. » read more

Accelerating Electrical Systems Design And Analysis With VeSys
By Mentor, a Siemens Business - 04 Nov, 2020 - Comments: 0

Electrical systems are constantly growing, whether in passenger cars, aircraft or heavy machinery. The growing size and complexity of these systems is driving up development costs and the likelihood of errors, potentially leading to even more cost or damaged brand reputation. New electrical systems and wiring harness engineering solutions implement automation, facilitate collaboration and accel... » read more

FPGA Prototyping Complexity Rising
By Ann Mutschler - 28 May, 2020 - Comments: 0

Multi-FPGA prototyping of ASIC and SoC designs allows verification teams to achieve the highest clock rates among emulation techniques, but setting up the design for prototyping is complicated and challenging. This is where machine learning and other new approaches are beginning to help. The underlying problem is that designs are becoming so large and complex that they have to be partitioned... » read more

Parasitic Extraction of MIM/MOM Capacitors In Analog/RF Designs
By Mentor, a Siemens Business - 26 Feb, 2020 - Comments: 0

The extensive use of MIM/MOM capacitors in analog/RF designs presents designers with extraction challenges that typically require multiple extraction techniques. The Calibre xACT platform offers analog/RF designers the fast performance of a rule-based extraction engine, and the capacity and performance of a field solver, to efficiently extract all parasitic components in a timely manner, with t... » read more

ATE Lab To Fab
By Ed Sperling - 05 Jun, 2019 - Comments: 2

Shu Li, business development manager at Advantest, zeroes in on the communication gap between engineers on the design side and the manufacturing/test side, why it exists, and what needs to be done to bridge that gap in order to speed up and improve test quality. https://youtu.be/Nd-5_twbJBw     See other tech talk videos here » read more

Verification At 7/5nm
By Ed Sperling - 25 Apr, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks about what’s missing in verification, how is that affected by complex chips such as 7nm SoCs or AI chips, and why more steps need to be done concurrently. https://youtu.be/bz6KyJh67sI » read more

eFPGA vs. FPGA Design Methodologies
By Ed Sperling - 05 Oct, 2018 - Comments: 0

Namit Varma, senior director of Achronix’s India Technology Center, discusses the differences between discrete and embedded FPGAs. https://youtu.be/Vwo3ktQvcKc » read more

Electromagnetic Analysis and Signoff: Cost Savings
By Magdy Abadir - 18 Sep, 2018 - Comments: 0

By Nikolas Provatas and Magdy Abadir We are often asked by SoC design teams about the benefits of an electromagnetic analysis and signoff methodology. Here is an overview of some of the big “cost savings”. Time to Market Savings Utilizing an EM crosstalk analysis and signoff methodology provides designers with an “insurance policy” against the risk of EM coupling in their SOC des... » read more

Accelerating SoC Time To Market With Cloud-Based Verification
By Cadence - 12 Sep, 2018 - Comments: 0

This paper discusses the growing use of cloud and hybrid cloud environments among semiconductor design and verification teams. The schedule and efficiency benefits seen by verification teams using cloud are specifically highlighted, due to the considerable compute requirements associated with verification of advanced node SoCs, and the significant impact verification has on the overall SoC proj... » read more

The Chiplet Race Begins
By Mark LaPedus - 06 Aug, 2018 - Comments: 1

Momentum is building for the development of advanced packages and systems using so-called chiplets, but the technology faces some challenges in the market. A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. In fact, the Defense Advanced Research Projects Agency (DARPA), part... » read more

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