Evaluation Platforms Key To Complex IP Integration

By Swamy Irrinki - 25 Sep, 2014 - Comments: 0

Just because a chip is complex to build doesn’t mean it has to take a long time. Runaway complexity in SoC and ASIC design is forcing chip companies to consider different methodologies and approaches that could actually simplify and speed up the whole process. The first step in this process was commercial IP, and its growing popularity attests to the fact that chipmakers are looking for... » read more

I Have Seen The Future

By Mike Gianfagna - 25 Sep, 2014 - Comments: 0

We recently concluded an online survey that measured design challenges and general sentiment regarding how they can be addressed, with some specific forward-looking queries. The title of the survey was “Big Data, the Cloud and Internet of (Silicon) Things.” We essentially asked our survey respondents to look into the future. We got an excellent response to this survey, with lots of thoughtf... » read more

Time To Market Concerns Worsen

By Ed Sperling - 25 Sep, 2014 - Comments: 1

Time to market has always been an issue for chipmakers in highly competitive sectors, but as complexity of chips continues to grow at advanced nodes, and as markets shift increasingly toward consumer electronics, it has jumped to the No. 1 concern. Interviews with engineers at multiple levels inside of some of the largest and midsize chipmakers, conducted by Semiconductor Engineering over th... » read more

There’s A New Paradigm In Town

By Kurt Shuler - 24 Oct, 2013 - Comments: 0

I recently wrote an article in the October 9th issue of EETimes that appears to have rattled the semiconductor industry a bit. Entitled “Wake Up, Semi Industry: System OEMs Might Not Need You,” the article conveyed the fact that many system-level OEMs now have the capability — and desire — to develop their own application-specific chips. This may be news to many. But a simple review... » read more

Experts At The Table: Next-Generation IP Landscape

By Ann Mutschler - 30 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Reducing Wait Time

By Tom De Schutter - 25 Apr, 2013 - Comments: 0

By Tom De Schutter Last month we were all waiting for white smoke to emerge from the chimney on the roof of the Sistine Chapel at the Vatican. I am of course talking about the election of the new pope. I couldn’t help but see a parallel with how software developers are anxiously waiting for their software to run correctly and finally get past the series of seemingly never ending bugs (black ... » read more

The New Platform-Based Design

By Ann Mutschler - 28 Feb, 2013 - Comments: 0

By Ann Steffora Mutschler Driven by the continued explosion in design costs, the term ‘platform-based design’ is evolving. A platform used to be viewed as an actual chip with some configurability on it that a semiconductor company promoted. Their customers would buy that chip in volume, configure it to their requirements, and sell it inside their end devices. The definition has beco... » read more

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tag: time-to-market

Evaluation Platforms Key To Complex IP Integration

I Have Seen The Future

Time To Market Concerns Worsen

There’s A New Paradigm In Town

Experts At The Table: Next-Generation IP Landscape

Reducing Wait Time

The New Platform-Based Design

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