tag: trace

Workload Trace Generation
By Arm - 13 Mar, 2024 - Comments: 0

The intended audience for this document is a performance engineer preparing traces for performance prediction on new Arm hardware. It is expected that the reader understands the basic concepts of performance engineering such as: • Workload characterization • Identifying key aspects of a workload • Understanding how Performance Monitor Unit (PMU) events correlate to a workload Click her... » read more

Efficient Trace In RISC-V
By Ed Sperling - 19 Dec, 2022 - Comments: 0

Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what's needed for debug and trace in context, including the need for unobtrusive observation at full speed, what to trace and when to trace it, and how embedded IP can identify to report which branches are tak... » read more

Manage Your Risk In RISC-V
By Peter Shields - 06 Dec, 2022 - Comments: 0

Adoption of RISC-V processors is accelerating. This technology, like everything, comes with benefits and risks. The open standard means freedom for many developers, but success depends on the development of a support ecosystem around RISC-V. Industry collaboration is making broad adoption of RISC-V possible, and one example is the introduction of efficient trace for RISC-V cores. When incorp... » read more

Bugs That Kill
By Brian Bailey - 23 Aug, 2018 - Comments: 3

Are simulation-resistant superbugs stifling innovation? That is a question Craig Shirley, president and CEO of Oski Technology, asked a collection of semiconductor executives over dinner. Semiconductor Engineering was invited to hear that discussion and to present the key points of the discussion. To promote free conversation, the participants, who are listed below, asked not to be quoted di... » read more

The Week In Review: Design
By Jesse Allen - 23 Feb, 2018 - Comments: 0

Tools & IP Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point ... » read more

Capturing The Future, Frame By Frame
By Stephen Barton - 25 May, 2017 - Comments: 0

A lot has changed over the past year, and more changes are on the way. Consider what's happening in API tracing. All of the functions from the Vulkan specification can be traced correctly in MGD. This means that you will be able to see exactly what Vulkan calls your application makes and in what order. You will also be able to see what threads each of these function calls occur in. Figu... » read more

Digging Into Trace Data
By Matt Sealey - 30 Jun, 2016 - Comments: 1

In previous blogs we covered an introduction to System Trace Macrocell (STM) concepts and terminology, and the STM Programmers' model with an example of how to generate efficient trace data. Once the STM is generating a trace stream, we may wish to view it within our Debugger. DS-5 implements an "Events View," which serves this purpose. Configuring your target First, it is necessary to... » read more

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