The Week In Review: Design

FPGA prototyping modules; 5G IP; RISC-V trace; Ansys, Synopsys results.


Tools & IP
Pro Design launched three new proFPGA Zynq UltraScale+ FPGA modules for SoC and IP prototyping. The modules combine FPGA logic with quad-core ARM Cortex-A53 and dual-core ARM Cortex-R5 processors and on-board interfaces. The modules offer a total of up to 5 extension sites with 531 standard I/Os and 16 multi-gigabit transceivers (MGTs). The board allows a maximum point-to-point speed of up to 1.2 Gbps over the standard FPGA I/Os and up to 16.3 Gbps over the MGTs.

Mentor Embedded Linux now supports the latest AMD Embedded processor families, EPYC Embedded 3000 and Ryzen Embedded V1000, targeting industrial, medical, networking, storage, and edge computing devices. MEL provides support for hardware-accelerated applications as well as advanced graphics, multimedia and video applications.

CEVA uncorked its 5G IP platform for enhanced mobile broadband (eMBB). PentaG is targeted at smartphones, fixed wireless access, and embedded devices that can take advantage of multi-gigabit data rates. It includes a combination of specialized scalar and vector DSP processors with an enhanced 5G ISA, specialized co-processors, accelerators, software and other IP blocks. It also features an AI processor to deliver up to 8X performance improvement for link adaptation workloads.

CEVA also debuted a new family of 802.11ax Wi-Fi IP targeting client devices, smart home, and network infrastructure with low power, high performance, and multi-gig configurations. CEVA says Wi-Fi 802.11ax provides 25% data rate improvements over 802.11ac as well as improvements to spectrum efficiency and network capacity.

SoC-e updated its Multiport Time Sensitive Networking Switch IP, adding support for 802.1AB LLDP (Link Layer Discovery Protocol), a software-implemented feature allows TSN devices to discover the topology of the network to which it is connected.

Aldec’s Active-HDL FPGA design and simulation software now supports QuickLogic’s eFPGAs. The tool includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for FPGA and eFPGA designs and will work with QuickLogic’s Aurora development tool suite.

UltraSoC and Lauterbach teamed up on an SoC development and debug environment that supports RISC-V. The solution includes UltraSoC’s embedded processor trace IP and Lauterbach’s TRACE32 modular development tools with integrated debug environments.

Galileo Satellite Navigation made its software-based Global Navigation Satellite System GPS receiver available for Cadence’s Tensilica Fusion F1 DSP. The GPS software requires less than 110MHz for full 12-satellite functionality.

Ansys reported fourth quarter financial results with revenue of $302.3 million, up 9% from Q4 last year. On a GAAP basis, earnings per share for the quarter stood at $0.61, down 24% from $0.80 per share for the same quarter last year. Non-GAAP earnings for Q4 2017 were $1.07 per share, up 9% from $0.98 per share in Q4 2016. For the whole of 2017, revenue was $1,095.3 million, up 10% from 2016. Earnings for the year, on a GAAP basis, were $2.98 per share, down less than 1% from $2.99 per share last year. Non-GAAP earnings were $4.01 per share, up 10% from $3.63 the previous year.

Synopsys released financial results for the first quarter of 2018 with revenue of $769.4 million, up 18% from the first quarter last year. On a GAAP basis, there was a loss per share of $0.02, down from income per share of $0.56 in the first quarter last year. Non-GAAP income for Q1 2018 was $1.10 per share, up 17% from $0.94 per share in Q1 2017.

Richard Weber is this year’s recipient of the Accellera Technical Excellence Award his technical contributions in helping to drive register descriptions among multiple working groups including SystemRDL, IP-XACT and UVM. Weber is the CEO of Semifore and has worked on register descriptions with many Accellera working groups for more than a decade.

Moortec appointed Mark Davitt as the company’s new sales representative for North America. Davitt was formerly the sales director for Sidense.

Arteris IP is making a push for ISO 26262 training and certification within the company, with 48 engineers earning the ISO 26262 Functional Safety Practitioner certification from Exidia.

FPGA 2018: Feb. 25-27 in Monterey, CA. The conference includes a workshop on packet processing with the P4 language, a panel and several presentations focused on machine learning, and a look at new architectures.

DVCon 2018: Feb. 26-Mar. 1 in San Jose, CA. Features include tutorials on the Portable Stimulus Standard and UVM, a keynote on how new segments in the industry are changing verification, and a new slate of short workshops. Brian Bailey takes a look at what to check out.

Embedded World 2018: Feb. 27-Mar. 1 in Nuremberg, Germany. The trade show and conference focused on embedded systems will feature keynotes on  embedded systems incorporating artificial intelligence, displays, and OLEDs.

ASICs Unlock Deep Learning Innovation: Mar. 14, 3:30 p.m. – 7:30 p.m., in Mountain View, CA. This seminar will explore an implementation platform for deep learning ASICs including HBM2 and 2.5D system-in-package design and implementation. The event is hosted by Samsung Electronics, Amkor, eSilicon, and Northwest Logic with a keynote by Ty Garibay, CTO of Arteris IP.

ISQED 2018: Mar. 13-14 in Santa Clara, CA. The conference highlights design techniques and methods, design processes, and EDA design methodologies and tools to improve the quality and manufacturability of ICs. Keynote speakers will address asymmetry in electronics, opportunities in AI, and recent materials and design innovations. Tutorials focus on power-aware test, power for IoT, and cyber-physical systems.

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