tag: transaction-level modeling

A HIL Methodology For The SoC Development Flow
By Technical Paper Link - 14 Nov, 2023 - Comments: 0

A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research Center for Artificial Intelligence (DFKI). Abstract: "Virtual Prototypes act as an executable specification model, offering a unified behavior reference model for SW and HW engineers. However, b... » read more

Anatomy Of A System Simulation
By Brian Bailey - 26 Oct, 2023 - Comments: 0

The semiconductor industry has greatly simplified analysis by consolidating around a small number of models and abstractions, but that capability is breaking down both at the implementation level and at the system level. Today, the biggest pressure is coming from the systems industry, where the electronic content is a small fraction of what must be integrated together. Systems companies tend... » read more

The Drive Toward Virtual Prototypes
By Brian Bailey - 22 Nov, 2022 - Comments: 1

Chipmakers are piling an increasing set of demands on virtual prototypes that go well beyond its original scope, forcing EDA companies to significantly rethink models, abstractions, interfaces, view orthogonality, and flows. The virtual prototype has been around for at least 20 years, but its role has been limited. It has largely been used as an integration and analysis platform for models t... » read more

RISC-V Virtual Prototype
By Technical Paper Link - 12 Oct, 2022 - Comments: 0

A new technical paper titled "Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype" was published by researchers at DFKI GmbH and University of Bremen. Abstract "RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet o... » read more

RISC-V: Advanced Virtual Prototyping Solutions
By Technical Paper Link - 23 May, 2022 - Comments: 0

New technical paper titled "Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges" from researchers at Institute of Computer Science, University of Bremen and Cyber-Physical Systems, DFKI GmbH. Abstract "Virtual prototypes (VPs) are crucial in today’s design flow. VPs are predominantly created in SystemC transaction-level modelin... » read more

High-Level Synthesis For RISC-V
By Brian Bailey - 28 Oct, 2021 - Comments: 2

High-quality RISC-V implementations are becoming more numerous, but it is the extensibility of the architecture that is driving a lot of design activity. The challenge is designing and implementing custom processors without having to re-implement them every time at the register transfer level (RTL). There are two types of high-level synthesis (HLS) that need to be considered. The first is ge... » read more

Which Verification Engine When
By Ed Sperling - 31 Oct, 2019 - Comments: 0

Frank Schirrmeister, group director for product marketing at Cadence, talks about which tools get used throughout the design flow, from architecture to simulation, formal verification, emulation, prototyping all the way to production, how the cloud has impacted the direction of the flow, and how machine learning will impact verification. » read more

Hybrid Emulation
By Brian Bailey - 29 Jun, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Say Hi To Hybrid
By Doug Amos - 29 Oct, 2015 - Comments: 0

It has been proposed for some time that virtual platforms could be linked to emulation hardware in order to co-verify the software and hardware components of an SoC. However, that proposal now has evolved into hybrid emulation, a practical solution to allow pre-silicon verification and validation of today’s complex SoC designs. First-rate work by the standards body Accellera and the Open ... » read more

Top 5 Trends For 2014
By Frank Schirrmeister - 19 Dec, 2013 - Comments: 0

My daughter’s and my traditional yearly cookie baking party last weekend reminded me of two things: There is still no easy recipe for system design and verification and – of course – the year is almost over again. Ouch. Let’s look back at 2013 first. Earlier this year we held a System to Silicon Verification Summit in San Jose, with an interesting technical keynote by Brian Bailey an... » read more

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