Understanding CFETs, A Next Generation Transistor Architecture

By Sam Sarkar - 23 May, 2024 - Comments: 0

Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more

The Impact Of Metal Gate Recess Profile On Transistor Resistance And Capacitance

By Pradeep Nanja - 18 May, 2023 - Comments: 0

In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal gate recess dimensions. However, there are limits to reducing this capacitance if you simply remove more of the metal material, since this can modify capacitance unexpectedly through chan... » read more

Reducing Contact Resistance in Developing Transistors Based On 2D Materials

By Technical Paper Link - 10 Mar, 2023 - Comments: 0

A new technical paper titled "WS2 Transistors with Sulfur Atoms Being Replaced at the Interface: First-Principles Quantum-Transport Study" was published by researchers at National Yang Ming Chiao Tung University. Abstract "Reducing the contact resistance is one of the major challenges in developing transistors based on two-dimensional materials. In this study, we perform first-principles ... » read more

How Low Can You Go? Pushing The Limits Of Transistors

By Synopsys - 08 Mar, 2023 - Comments: 0

Deep low voltage enablement of embedded memories and logic libraries to achieve extreme low power: Rising demand for cutting-edge mobile, IoT, and wearable devices, along with high compute demands for AI and 5G/6G communications, has driven the need for lower power systems-on-chip (SoCs). This is not only a concern for a device’s power consumption when active (dynamic power), but also when... » read more

Asynchronously Parallel Optimization Method For Sizing Analog Transistors Using Deep Neural Network Learning

By Technical Paper Link - 03 Mar, 2023 - Comments: 0

A new technical paper titled "APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors Using DNN Learning" was published by researchers at UT Austin and Analog Devices. Abstract "Analog circuit sizing is a high-cost process in terms of the manual effort invested and the computation time spent. With rapidly developing technology and high market demand, bringing automated s... » read more

Biocompatible Bilayer Graphene-Based Artificial Synaptic Transistors (BLAST) Capable of Mimicking Synaptic Behavior

By Technical Paper Link - 10 Aug, 2022 - Comments: 0

This new technical paper titled "Metaplastic and energy-efficient biocompatible graphene artificial synaptic transistors for enhanced accuracy neuromorphic computing" was published by researchers at The University of Texas at Austin and Sandia National Laboratories. Abstract "CMOS-based computing systems that employ the von Neumann architecture are relatively limited when it comes to para... » read more

Improved graphene-base heterojunction transistor with different collector semiconductors for high-frequency applications

By Technical Paper Link - 10 Apr, 2022 - Comments: 0

New research paper from TU Dresden & others. Abstract "A new kind of transistor device with a graphene monolayer embedded between two n-typesilicon layers is fabricated and characterized. The device is called graphene-base heterojunction transistor (GBHT). The base-voltage controls the current of the device flowing from the emitter via graphene to the collector. The transit time for e... » read more

Transition-Metal Nitride Halide Dielectrics for Transition-Metal Dichalcogenide Transistors

By Technical Paper Link - 20 Dec, 2021 - Comments: 0

Abstract "Using first-principles calculations, we investigate six transition-metal nitride halides (TMNHs): HfNBr, HfNCl, TiNBr, TiNCl, ZrNBr, and ZrNCl as potential van der Waals (vdW) dielectrics for transition metal dichalcogenide (TMD) channel transistors. We calculate the exfoliation energies and bulk phonon energies and find that the six TMNHs are exfoliable and thermodynamically stabl... » read more

Power/Performance Bits: March 31

By Jesse Allen - 31 Mar, 2020 - Comments: 0

Tellurium transistors Researchers from Purdue University, Washington University in St Louis, University of Texas at Dallas, and Michigan Technological University propose the rare earth element tellurium as a potential material for ultra-small transistors. Encapsulated in a nanotube made of boron nitride, tellurium helps build a field-effect transistor with a diameter of two nanometers. �... » read more

The 7nm Pileup

By Ed Sperling - 04 Apr, 2019 - Comments: 1

The number of 7nm designs is exploding. Cadence alone reports 80 new 7nm chips under design. So why now, and what does this all mean? First of all, 7nm appears to be the next 28nm. It's a major node, and it intersects with a number of broad trends that are happening across the industry, all of which involve AI in one way or another. The big question now is how many of them will survive long ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?