tag: TU Dresden

ReRAM-Based, In-Memory Implementation Of Stochastic Computing
By Technical Paper Link - 14 Apr, 2025 - Comments: 0

A new technical paper titled "All-in-Memory Stochastic Computing using ReRAM" was published by researchers at TU Dresden, Center for Scalable Data Analytics and Artificial Intelligence (ScaDS.AI), Case Western Reserve University, University of Louisiana at Lafayette and Barkhausen Institut. Abstract "As the demand for efficient, low-power computing in embedded and edge devices grows, tradit... » read more

Chip Industry Technical Paper Roundup: Feb. 18
By Linda Christensen - 18 Feb, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=406 /] Find all technical papers here. » read more

Modeling and Simulation of NVM Technologies: Tutorial (TU Dormand, TU Dresden, KIT, FAU)
By Technical Paper Link - 17 Feb, 2025 - Comments: 0

A new technical paper titled "Modeling and Simulating Emerging Memory Technologies: A Tutorial" was published by researchers at TU Dortmund, TU Dresden, Karlsruhe Institute of Technology (KIT) and FAU ErlangenNürnberg. "This tutorial presents a simulation toolchain through four detailed case studies, showcasing its applicability to various domains of system design, including hybrid main-mem... » read more

Schottky Barrier Transistors: Status, Challenges and Modeling Tools
By Technical Paper Link - 08 Jan, 2025 - Comments: 0

A technical paper titled "Roadmap for Schottky barrier transistors" was published by researchers at University of Surrey, Namlab gGmbH, Forschungszentrum Jülich (FZJ), et al. Abstract "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier (SB), as an asset for device functio... » read more

Research Bits: July 22
By Jesse Allen - 22 Jul, 2024 - Comments: 0

Sub-1nm gate Researchers from Korea's Institute for Basic Science, Sungkyunkwan University, Harvard University, and Korea Advanced Institute of Science and Technology (KAIST) found a method that enables epitaxial growth of 1D metallic materials with a width of less than 1 nm, which they used as a gate electrode of a miniaturized transistor. The team controlled the crystal structure of molyb... » read more

Chip Industry Technical Paper Roundup: July 22
By Linda Christensen - 22 Jul, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=245 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review
By The SE Staff - 19 Jul, 2024 - Comments: 0

The University of Texas at Austin’s Texas Institute for Electronics (TIE) was awarded $840 million to establish a Department of Defense microelectronics manufacturing center. This center will focus on developing advanced semiconductor microsystems to enhance U.S. defense systems. The project is part of DARPA's NGMM Program. The U.S. Dept. of Commerce announced preliminary terms with Global... » read more

HW Security: Flip-Flops Along Logic Gates to Prevent Synthesis Tools’ Structural Leakages (TU Dresden, Ruhr Univ. Bochum)
By Technical Paper Link - 17 Jul, 2024 - Comments: 0

A new technical paper titled "Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks" was published by researchers at TU Dresden and Ruhr University Bochum. Abstract "Machine learning (ML) and algorithmic structural attacks have highlighted the possibility of utilizing structural leakages of an obfuscated circuit to reverse engineer th... » read more

Chip Industry Technical Paper Roundup: March 26
By Linda Christensen - 26 Mar, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=209 /] Find last week's technical paper additions here. » read more

Band-To-Band Tunneling And Negative Differential Resistance in Heterojunctions Built Entirely Using 2D Materials
By Technical Paper Link - 15 Mar, 2024 - Comments: 0

A technical paper titled "Electrical characterization of multi-gated WSe2 /MoS2 van der Waals heterojunctions" was published by researchers at Helmholtz-Zentrum Dresden Rossendorf (HZDR), TU Dresden, National Institute for Materials Science (Japan) and NaMLab gGmbH. Abstract "Vertical stacking of different two-dimensional (2D) materials into van der Waals heterostructures exploits the pr... » read more

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