tag: UC Berkeley

Design Considerations and Recent Advancements in Chiplets (UC Berkeley/ Peking University)
By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "Automated Design of Chiplets" was published by researchers at UC Berkeley and Peking University. Abstract: "Chiplet-based designs have gained recognition as a promising alternative to monolithic SoCs due to their lower manufacturing costs, improved re-usability, and optimized technology specialization. Despite progress made in various related domains, the des... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 03 Mar, 2023 - Comments: 0

Semiconductor Research Corporation (SRC) released an interim roadmap for Microelectronic and Advanced Packaging Technologies (MPAT) that targets 10- to 15-year goals for 3D integration and multi-chiplet packaging. The roadmap is open for comments. Participants in the MPAT include AMD, IBM, Intel, Texas Instruments, Purdue University, SUNY Binghamton and the Georgia Institute of Technology. It i... » read more

Is UCIe Really Universal?
By Brian Bailey - 22 Nov, 2022 - Comments: 3

Chiplets are rapidly becoming the means to overcome the slowing of Moore's Law, but whether one interface is capable of joining them all together isn't clear yet. The Universal Chiplet Interconnect Express (UCIe) believes it will work, but some in the industry remain unconvinced. At least part of the problem is that interconnect standards are never truly finished. Even today, the protocols tha... » read more

Week In Review: Semiconductor Manufacturing, Test
By Karen Heyman - 21 Oct, 2022 - Comments: 0

Fallout from the new U.S. export controls continues. Under new regulations, companies looking to supply Chinese chipmakers with advanced manufacturing equipment (<14nm) must first obtain a license from the U.S. Department of Commerce. In addition, U.S. persons (citizens and permanent residents) are barred from supporting China’s advanced chip development or production without a license. ... » read more

Blog Review: Oct. 5
By Jesse Allen - 05 Oct, 2022 - Comments: 0

Arm's Andrew Pickard chats with Georgia Tech's Azad Naeemi and Da Eun Shim about an effort to evaluate the benefit of new interconnect materials and wire geometry and determine their impacts at the microprocessor level. Synopsys' Shekhar Kapoor shares highlights from a recent panel exploring the promises, challenges, and realities of 3D IC technology, including the potential of 3D nanosystem... » read more

Research Bits: Oct. 4
By Jesse Allen - 04 Oct, 2022 - Comments: 0

2D electrode for ultra-thin semiconductors Researchers from the Korea Institute of Science and Technology (KIST), Japan's National Institute for Materials Science, and Kunsan National University designed two-dimensional semiconductor-based electronic and logic devices, with electrical properties that can be selectively controlled through a new 2D electrode material, chlorine-doped tin diseleni... » read more

The Next Incarnation Of EDA
By Brian Bailey - 25 Aug, 2022 - Comments: 0

The EDA industry has incrementally addressed issues as they arise in the design of electronic systems, but is there about to be a disruption? Academia is certainly seeing that as a possibility, but not all of them see it happening for the same reason. The academic community questioned the future of EDA at the recent Design Automation Conference. Rather than EDA as we know it going away, they... » read more

Technical Paper Round-Up: Aug 23
By Linda Christensen - 23 Aug, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=46 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Gemmini: Open-source, Full-Stack DNN Accelerator Generator (DAC Best Paper)
By Technical Paper Link - 19 Aug, 2022 - Comments: 0

This technical paper titled "Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration" was published jointly by researchers at UC Berkeley and a co-author from MIT.  The research was partially funded by DARPA and won DAC 2021 Best Paper. The paper presents Gemmini, "an open-source, full-stack DNN accelerator generator for DNN workloads, enabling end-to-e... » read more

Technical Paper Round-Up: July 18
By Linda Christensen - 18 Jul, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit fo... » read more

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