tag: UC Berkeley

Gemmini: Open-source, Full-Stack DNN Accelerator Generator (DAC Best Paper)
By Technical Paper Link - 19 Aug, 2022 - Comments: 0

This technical paper titled "Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration" was published jointly by researchers at UC Berkeley and a co-author from MIT.  The research was partially funded by DARPA and won DAC 2021 Best Paper. The paper presents Gemmini, "an open-source, full-stack DNN accelerator generator for DNN workloads, enabling end-to-e... » read more

Technical Paper Round-Up: July 18
By Linda Christensen - 18 Jul, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=33 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit fo... » read more

MIT & UC Berkeley: “Exo” Programming Language Writes High Performance Code For HW Accelerators
By Technical Paper Link - 11 Jul, 2022 - Comments: 0

New research paper titled "Exocompilation for productive programming of hardware accelerators," from researchers at MIT and UC Berkeley. From their abstract: "To better support development of high-performance libraries for specialized hardware, we propose a new programming language, Exo, based on the principle of exocompilation: externalizing target-specific code generation support and op... » read more

Week In Review, Manufacturing, Test
By Karen Heyman - 01 Jul, 2022 - Comments: 0

Samsung announced initial production of its 3nm process node, which uses a gate-all-around (nanosheet) transistor structure that the company calls Multi-Bridge-Channel FET (MBCFET). The first-generation 3nm process can reduce power consumption by up to 45% compared with a 5nm process, as well as improve performance by 23% and reduce area by 16%, according to the company. The second-generation 3... » read more

Technical Paper Round-Up: June 28
By Linda Christensen - 28 Jun, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=35 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Designing Hardware Accelerators Using A Data-Driven Approach
By Technical Paper Link - 21 Jun, 2022 - Comments: 0

Research paper titled "Data-Driven Offline Optimization For Architecting Hardware Accelerators" by researchers at Google Research and UC Berkeley. Abstract "Industry has gradually moved towards application-specific hardware accelerators in order to attain higher efficiency. While such a paradigm shift is already starting to show promising results, designers need to spend considerable man... » read more

Technical Paper Round-up: May 31
By Linda Christensen - 31 May, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=30 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Using Dynamic Route Map Technique for Insight Into Memristors
By Technical Paper Link - 24 May, 2022 - Comments: 0

New technical paper titled "Empirical Characterization of ReRAM Devices Using Memory Maps and a Dynamic Route Map," from Balearic Islands University, UC Berkeley, Health Institute of the Balearic Islands, International Hellenic University, Technische Universität Dresden, Universidad de Valladolid, and Aristotle University of Thessaloniki. Abstract: "Memristors were proposed in the early 1... » read more

Architecting Faster Computers
By Brian Bailey - 14 Apr, 2022 - Comments: 3

To create faster computers, the industry must take a major step back and re-examine choices that were made half a century ago. One of the most likely approaches involves dropping demands for determinism, and this is being attempted in several different forms. Since the establishment of the von Neumann architecture for computers, small, incremental improvements have been made to architectures... » read more

Planning EDA’s Next Steps
By Ed Sperling - 24 Mar, 2022 - Comments: 0

Anirudh Devgan, Cadence's new CEO, and the recipient of the Phil Kaufman Award in December, sat down with Semiconductor Engineering to talk about what's next in EDA, the underlying technology and business challenges and changes, and new markets that are unfolding for floor-planning, verification, CFD, and advanced packaging. SE: Where does EDA need to improve? Devgan: We have made it much... » read more

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