Chiplet Tradeoffs And Limitations


The semiconductor industry is buzzing with the benefits of chiplets, including faster time to market, better performance, and lower power, but finding the correct balance between customization and standardization is proving to be more difficult than initially thought. For a commercial chiplet marketplace to really take off, it requires a much deeper understanding of how chiplets behave indiv... » read more

Unleashing AI Potential Through Advanced Chiplet Architectures


The rapid proliferation of machine-generated data is driving unprecedented demand for scalable AI infrastructure, placing extreme pressure on compute and connectivity within data centers. As the power requirements and carbon footprint of AI workloads rise, there is a critical need for efficient, high-performance hardware solutions to meet growing demands. Traditional monolithic ICs will not sca... » read more

Chiplets: A Technology, Not A Market


Chiplets are big business, and that business is growing. The total chiplet market today is roughly $40 billion annually. Chiplets account for roughly 15% of TSMC's revenues, and they account for about 25% of all DRAMs. All of the major AI/HPC semiconductor companies (NVIDIA, AMD, Marvell, Broadcom) and the major hyper scalers (Amazon, Google, etc) are looking to chiplets to build superior... » read more

Multi-Die Health And Reliability: UCIe Advances


Although multi-die designs — an increasingly popular approach for integrating heterogeneous and homogenous dies into a single package — help resolve problems related to chip manufacturing and yield, they introduce a host of complexities and variables that must be addressed. In particular, designers must work diligently to ensure the health and reliability of their multi-die chip throughout ... » read more

Signal Integrity Plays Increasingly Critical Role In Chiplet Design


Maintaining the quality and reliability of electrical signals as they travel through interconnects is proving to be much more challenging with chiplets and advanced packaging than in monolithic SoCs and PCBs. Signal integrity is a fundamental requirement for all chips and systems, but it becomes more difficult with chiplets due to reflections, loss, crosstalk, process variation, and various ... » read more

UCIe For 1.6T Interconnects In Next-Gen I/O Chiplets For AI Data Centers


The rise of generative AI is pushing the limits of computing power and high-speed communication, posing serious challenges as it demands unprecedented workloads and resources. No single design can be optimized for the different classes of models – whether the focus is on compute, memory bandwidth, memory capacity, network bandwidth, latency sensitivity, or scale, all of which are affected by ... » read more

What’s Missing From Predictions


At this point everyone has made their predictions for the year, but there is one thing many people get wrong. Predictions are not about innovation. They are about pain and what is causing it. This industry is risk-averse, and everyone wants to continue doing what they are doing. But there comes a point when it's so painful to continue that something has to change. Having something that is... » read more

Chiplets Still A Challenge With UCIe 2.0


Plug-and-play chiplets are a popular goal, but does UCIe 2.0 move us any closer to that becoming a reality? The problem is that the current drivers of the standard are not after interoperability in the way that plug-and-play requires. Released in August 2024, UCIe 2.0 touts higher bandwidth density and improved power efficiency, as well as new features supporting 3D packaging, a manageable s... » read more

Advanced Packaging Moving At Breakneck Pace


Experts at the Table: Semiconductor Engineering sat down to discuss advances in packaging with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. [Part 2 of the discussion is here.] ... » read more

Integrating Ethernet, PCIe, And UCIe For Enhanced Bandwidth And Scalability For AI/HPC Chips


By Madhumita Sanyal and Aparna Tarde Multi-die architectures are becoming a pivotal solution for boosting performance, scalability, and adaptability in contemporary data centers. By breaking down traditional monolithic designs into smaller, either heterogeneous or homogeneous dies (also known as chiplets), engineers can fine-tune each component for specific functions, resulting in notable im... » read more

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