Are Larger Reticle Sizes On The Horizon?


Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits or a wholesale change to larger masks. Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6x6-inch to 6x11-inch masks that would eliminate stitching, but it... » read more

Chip Industry Technical Paper Roundup: Apr. 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=416 /] Find more semiconductor research papers here. » read more

Evaluation Tool For The Cost Impacts Of Chiplet-Specific Design Choices


A new technical paper titled "CATCH: a Cost Analysis Tool for Co-optimization of chiplet-based Heterogeneous systems" was published by researchers at UCLA, Duke University and Arizona State University. Abstract "With the increasing prevalence of chiplet systems in high-performance computing applications, the number of design options has increased dramatically. Instead of chips defaulting to... » read more

Chip Industry Technical Paper Roundup: Mar. 25


New technical papers recently added to Semiconductor Engineering’s library: [table id=415 /] Find more semiconductor research papers here. » read more

Review Of Recent Advancements in THz-based 6G: Devices, Circuits, Antennas and Packaging


A new technical paper titled "A Survey on Advancements in THz Technology for 6G: Systems, Circuits, Antennas, and Experiments" was published by UCLA. Abstract "Terahertz (THz) carrier frequencies (100 GHz to 10 THz) have been touted as a source for unprecedented wireless connectivity and high-precision sensing, courtesy of their wide bandwidth availability and small wavelengths. However, no... » read more

Chip Industry Week In Review


Worldwide silicon wafer shipments declined nearly 2.7% to 12,266 million square inches in 2024, with wafer revenue contracting 6.5% to $11.5 billion, according to the SEMI Silicon Manufacturers Group. CSIS released a new report, “Critical Minerals and the Future of the U.S. Economy,” with detailed analysis and policy recommendations for building a secure mineral supply chain for semicond... » read more

Chip Industry Technical Paper Roundup: Jan. 20


New technical papers recently added to Semiconductor Engineering’s library: [table id=398 /] Find all technical papers here. » read more

Design-Space Analysis of M3D FPGA With BEOL Configuration Memories (Georgia Tech, UCLA)


A new technical paper titled "Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories" was published by researchers at Georgia Tech and UCLA. Abstract "This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power ef... » read more

Chip Industry Technical Paper Roundup: Nov. 11


New technical papers recently added to Semiconductor Engineering’s library: [table id=381 /] More Reading Technical Paper Library » read more

Visualization of Photoexcited Charges Moving Across the Interface of Si/Ge


A technical paper titled "Imaging hot photocarrier transfer across a semiconductor heterojunction with ultrafast electron microscopy" was published by researchers at UC Santa Barbara and UCLA. "In this work, we apply scanning ultrafast electron microscopy to provide a holistic view of photoexcited charge dynamics in a Si/Ge heterojunction. We find that the built-in potential and the band off... » read more

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