Chip Industry Technical Paper Roundup: July 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=445 /] Find more semiconductor research papers here. » read more

Data-Driven Approach To Power Modeling For DVFS-Enabled Heterogeneous Systems (ETH Zurich et al.)


A technical paper titled "Data-driven power modeling and monitoring via hardware performance counter tracking" was published by researchers at ETH Zürich, Scuola Superiore Sant’Anna, RISE Research Institutes of Sweden and University of Bologna. Abstract "Energy-centric design is paramount in the current embedded computing era: use cases require increasingly high performance at an afforda... » read more

Chip Industry Technical Paper Roundup: June 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=442 /] Find more semiconductor research papers here. » read more

Domain Adaptation for Image Classification of Defects in Semiconductor Manufacturing (Infineon, U. Padova et al.)


A new technical paper titled "Domain Adaptation for Image Classification of Defects in Semiconductor Manufacturing" was published by researchers at Infineon Technologies, University of Padova and University of Bologna. Abstract "In the semiconductor sector, due to high demand but also strong and increasing competition, time to market and quality are key factors in securing significant marke... » read more

Chip Industry Technical Paper Roundup: Feb. 10


New technical papers recently added to Semiconductor Engineering’s library: [table id=405 /] Find all technical papers here. Also find more research and latest news here. » read more

Optimization of the Inter-Chiplet Interconnect And The Chiplet Placement (ETH Zurich, U. of Bologna)


A new technical paper titled "PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies" was published by researchers at ETH Zurich and University of Bologna. Abstract "2.5D integration technology is gaining traction as it copes with the exponentially growing design cost of modern integrated circuits. A crucial part of a 2.5D stacked chip is a low-latency and high-throughput inter-ch... » read more

Chip Industry Technical Paper Roundup: Jan. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=395 /] Find all technical papers here. » read more

Designing Heterogeneous AI Acceleration SoCs


A new technical paper titled "Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience" was published by researchers at University of Bologna. Abstract "Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-source. Its portfolio now ranges from processor co... » read more

Chip Industry Technical Paper Roundup: Oct. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=375 /] More Reading Chip Industry Week In Review Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion. Technical Paper Library home » read more

Open-Source, Chiplet-Compatible RISC-V Controller


A new technical paper titled "ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package" was published by researchers at ETH Zurich and University of Bologna. Abstract "The increasing complexity of real-time control algorithms and the trend toward 2.5D technology necessitate the development of scalable controllers for managing the complex, integrated oper... » read more

← Older posts