Chip Industry’s Technical Paper Roundup: October 31

By Liz Allan - 31 Oct, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=159 /] More Reading Technical Paper Library home » read more

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling

By Technical Paper Link - 24 Oct, 2023 - Comments: 0

A technical paper titled “Enabling HW-based Task Scheduling in Large Multicore Architectures” was published by researchers at Barcelona Supercomputing Center, University of Campinas, University of Sao Paulo, and Arteris Inc. Abstract: "Dynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent... » read more

Research Bits: June 8

By Jesse Allen - 08 Jun, 2022 - Comments: 0

Five-second coherence for silicon carbide qubits Researchers from the University of Chicago, National Institutes for Quantum Science and Technology, and Linköping University built a qubit from silicon carbide and was able to retain its coherence, or the length of time the quantum state persists, for over five seconds. “It’s uncommon to have quantum information preserved on these human ... » read more

System Bits: May 6

By Jeff Dorsch - 06 May, 2019 - Comments: 0

Transmitting data with a semiconductor laser Researchers at the Harvard John A. Paulson School of Engineering and Applied Sciences demonstrated a laser that can emit microwaves wirelessly, modulate them, and receive external radio frequency signals. “The research opens the door to new types of hybrid electronic-photonic devices and is the first step toward ultra-high-speed Wi-Fi,” said ... » read more

System Bits: June 26

By Ann Mutschler - 26 Jun, 2018 - Comments: 0

I’m enjoying a very busy Design Automation Conference this week in San Francisco, and on the lookout for interesting research topics here. In the meantime, enjoy a few interesting items from around the globe. AI platform diagnoses Zika and other pathogens University of Campinas (UNICAMP) researchers in Brazil have developed an AI platform that can diagnose several diseases with a high deg... » read more

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Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: University of Campinas

Chip Industry’s Technical Paper Roundup: October 31

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling

Research Bits: June 8

System Bits: May 6

System Bits: June 26

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Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

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Entities, people and technologies explored

Related Articles

Partitioning In The Chiplet Era

3.5D: The Great Compromise

Legacy Process Nodes Going Strong

AI’s Role In Chip Design Widens, Drawing In New Startups

Key Technologies To Extend EUV To 14 Angstroms

Memory Fundamentals For Engineers

What Comes After HBM For Chiplets

Why Small Fab And Assembly Houses Are Thriving

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tag: University of Campinas

Chip Industry’s Technical Paper Roundup: October 31

FPGA-Proven RISC-V System With Hardware Accelerated Task Scheduling

Research Bits: June 8

System Bits: May 6

System Bits: June 26

Trending Articles

Hybrid Bonding Makes Strides Toward Manufacturability

Americas Chip Funding Energizes Industry

Advanced Packaging Driving New Collaboration Across Supply Chain

Chiplets Make Progress Using Interconnects As Glue

2D Semiconductors Make Progress, But So Does Silicon

Knowledge Centers Entities, people and technologies explored

Related Articles

Partitioning In The Chiplet Era

3.5D: The Great Compromise

Legacy Process Nodes Going Strong

AI’s Role In Chip Design Widens, Drawing In New Startups

Key Technologies To Extend EUV To 14 Angstroms

Memory Fundamentals For Engineers

What Comes After HBM For Chiplets

Why Small Fab And Assembly Houses Are Thriving

Sponsors

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Knowledge Centers
Entities, people and technologies explored