EMEA Investments Driving Technology Specialization

By Liz Allan - 04 Nov, 2024 - Comments: 0

Government programs across Europe and the UK are seeing a surge of investments in leading edge technology, materials, and packaging. Industry and academia are coalescing around specialty areas, drawing on established relationships to foster innovation and fill gaps in regional supply chains while also maintaining international bonds. Government initiatives also are picking up in Israel, Saudi A... » read more

Chip Industry Technical Paper Roundup: June 10

By Linda Christensen - 10 Jun, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=232 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review

By The SE Staff - 07 Jun, 2024 - Comments: 0

Rapidus and IBM are jointly developing mass production capabilities for chiplet-based advanced packages. The collaboration builds on an existing agreement to develop 2nm process technology. Vanguard and NXP will jointly establish VisionPower Semiconductor Manufacturing Company (VSMC) in Singapore to build a $7.8 billion, 12-inch wafer plant. This is part of a global supply chain shift “Out... » read more

Using Formal Verification To Evaluate The HW Reliability Of A RISC-V Ibex Core In The Presence Of Soft Errors

By Technical Paper Link - 31 May, 2024 - Comments: 0

A technical paper titled “Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core” was published by researchers at University of Southampton. Abstract: "Reliability has been a major concern in embedded systems. Higher transistor density and lower voltage supply increase the vulnerability of embedded systems to soft errors. A Single Event Upset (SEU), which is also calle... » read more

Chip Industry’s Technical Paper Roundup: Dec 5

By Linda Christensen - 05 Dec, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=171 /] More ReadingTechnical Paper Library home » read more

Front-end patterning and epitaxy approach on Si photonics 220nm SOI substrates

By Technical Paper Link - 29 Nov, 2023 - Comments: 0

A new technical paper titled "Lateral Tunnel Epitaxy of GaAs in Lithographically Defined Cavities on 220 nm Silicon-on-Insulator" was published by researchers at Cardiff University and University of Southampton. Abstract "Current heterogeneous Si photonics usually bond III–V wafers/dies on a silicon-on-insulator (SOI) substrate in a back-end process, whereas monolithic integration by di... » read more

Week In Review: Design, Low Power

By Susan Rambo - 28 Jul, 2023 - Comments: 0

Arm is helping to address the ongoing talent shortage through its newly announced Semiconductor Education Alliance, with a long list of partners, including Arduino, Cadence, Cornell University, Semiconductor Research Corp., STMicroelectronics,Synopsys, Taiwan Semiconductor Research Institute, the All-India Council for Technical Education, and the University of Southampton. The Alliance... » read more

Week In Review: Auto, Security, Pervasive Computing

By Liz Allan - 16 Jun, 2023 - Comments: 0

The European Parliament took a major step toward enacting the world’s first laws around the use of AI. Known as the AI Act, the draft law won a majority vote following two years of debate. If the proposed regulations pass the next hurdles, AI systems posing an unacceptable risk to human safety would be banned — along with “intrusive and discriminatory” uses of AI, including biometric su... » read more

Chip Industry’s Technical Paper Roundup: Apr. 4

By Linda Christensen - 04 Apr, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=90 /] If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us p... » read more

Large Area Process For Atomically Thin 2D Semiconductor, Using Scalable ALD

By Technical Paper Link - 30 Mar, 2023 - Comments: 0

A new technical paper titled "Large-area synthesis of high electrical performance MoS2 by a commercially scalable atomic layer deposition process" by researchers at the University of Southampton, LMU Munich, and VTT Technical Research Centre of Finland. Abstract: "This work demonstrates a large area process for atomically thin 2D semiconductors to unlock the technological upscale required... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?