Tech Talk: Improving Verification

By Ann Mutschler - 26 Apr, 2018 - Comments: 0

Frank Schirrmeister, senior group director for product management and marketing at Cadence, discusses how to verify different use cases, focusing on software, low-power designs, connectivity, and a variety of end markets. https://youtu.be/gK-0vmIWxJs » read more

Tech Talk: 5G

By Ed Sperling - 01 Feb, 2018 - Comments: 0

Mike Fitton, senior director of strategic planning at Achronix, talks about the new wireless standard, which will make its debut at the Winter Olympics, when it will go mainstream, and what kinds of technical issues need to be addressed to make that happen. https://youtu.be/tUEMKZpbN2Y » read more

Use Model Versatility: Key To Return On Investment For Emulation

By Frank Schirrmeister - 26 Oct, 2017 - Comments: 0

When we announced Palladium Z1 now almost two years ago in November 2015, we emphasized versatility of use models as a key component to optimize return on investment when adopting emulation. Today, our biggest customers are using emulation as a compute resource with 10s of projects in parallel, and they are running a large number of different use models on it. This year alone, more than 30 cust... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: use models

Tech Talk: Improving Verification

Tech Talk: 5G

Use Model Versatility: Key To Return On Investment For Emulation