tag: UVM

Gaps In The Verification Flow
By Brian Bailey - 29 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

The Future of UVM
By Neil Johnson - 26 Aug, 2016 - Comments: 7

It’s time for a frank discussion on the future of [gettech id="31055" comment="UVM"]. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to use UVM the right thing to do? Do we have hard evidence that supports our continued usage of UVM? Do we actually benefit from it or do we just think we benefit? ... » read more

Optimizing Testbench Acceleration Performance
By Mentor, a Siemens Business - 10 Aug, 2016 - Comments: 0

Part 3 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Making Verification Easier
By Ann Mutschler - 28 Jul, 2016 - Comments: 0

SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

What’s Next For UVM?
By Brian Bailey - 28 Jul, 2016 - Comments: 0

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

Testbench Acceleration Performance Demystified
By Mentor, a Siemens Business - 13 Jul, 2016 - Comments: 0

Part 2 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Executive Insight: Raik Brinkmann
By Ed Sperling - 06 Jul, 2016 - Comments: 0

[getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"], sat down with Semiconductor Engineering to discuss where and why formal verification is gaining traction, and how it fits alongside other verification approaches. What follows are excerpts of that conversation. SE: [getkc id="33" kc_name="Formal"] has been around for a whi... » read more

The UVM Configuration Database
By Henry Chan - 30 Jun, 2016 - Comments: 0

When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future. A database works much the same way, a collection of information that is stored and accessed on demand. Take the UVM configuration database for example. It basically acts as a repository so that when the... » read more

Can Verification Meet In The Middle?
By Brian Bailey - 30 Jun, 2016 - Comments: 0

Since the dawn of time for the EDA industry, the classic V diagram has defined the primary design flow. On the left hand side of the V, the design is progressively refined and partitioned into smaller pieces. At the bottom of the V, verification takes over and as you travel up the right-hand side of the V, verification and integration happens until the entire design has been assembled and valid... » read more

Reducing Design Risk With Testbench Acceleration
By Mentor, a Siemens Business - 29 Jun, 2016 - Comments: 0

Part 1 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy