Hybrid Emulation

By Brian Bailey - 29 Jun, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss the growing usage of hybrid verification approaches with Frank Schirrmeister, senior group director of product management & marketing for [getentity id="22032" e_name="Cadence"]; Russ Klein, program director for pre-silicon debug products at [getentity id="22017" e_name="Mentor, a Siemens Business"]; [getperson id="11027" comment="Phil Moorby"],... » read more

Safety Plus Security: A New Challenge

By Brian Bailey - 08 Jun, 2017 - Comments: 0

Nobody has ever integrated safety or security features into their design just because they felt like it. Usually, successive high-profile attacks are needed to even get an industry's attention. And after that, it's not always clear how to best implement solutions or what the tradeoffs are between cost, performance, and risk versus benefit. Putting safety and security in the same basket is a ... » read more

It’s Show Time

By Henry Chan - 25 May, 2017 - Comments: 0

It’s been a busy season. The weather has warmed here in the desert and as the trees and greenery enliven in spring, The whole industry is bursting with activity. From DVCon to the International Symposium on FPGAs in the United States to Embedded World and CTIC in Europe, there have been a number of important developments in verification, embedded systems, and DO-254. The DVCon U.S. Confere... » read more

Verification Unification

By Brian Bailey - 25 May, 2017 - Comments: 0

There is a lot of excitement about the emerging [getentity id="22028" e_name="Accellera"] [getentity id="22863" e_name="Portable Stimulus”] (PS) standard. Most of the conversation has been about its role in [getkc id="11" kc_name="simulation"] and [getkc id="30" kc_name="emulation"] contexts, and in the need to bring portability and composability into the verification flow. Those alone are st... » read more

Whatever Happened to High-Level Synthesis?

By Brian Bailey - 16 May, 2017 - Comments: 0

A few years ago, [getkc id="105" comment="high-level synthesis"] (HLS) was probably the most talked about emerging technology that was to be the heart of a new [getkc id="48" kc_name="Electronic System Level"] (ESL) flow. Today, we hear much less about the progress being made in this area. Semiconductor Engineering sat down to discuss this with Bryan Bowyer, director of engineering for high lev... » read more

Rediscovering Coverage Insurance

By Dave Kelf - 27 Apr, 2017 - Comments: 0

When coverage comes up in conversation, if it comes up at all, it’s always a matter of car, home or health insurance. Coverage and functional verification are unlikely to be used in that discussion, or any other for that matter. That’s too bad because engineering groups grapple with when is enough verification enough, like some kind of coverage insurance. Oh sure, simulation and emulatio... » read more

The Week In Review: Design

By Jesse Allen - 14 Apr, 2017 - Comments: 0

M&A Synapse Design acquired Asilicon, a design services firm based in Ranchi Jharkhand, India. Through the acquisition, Synapse Design adds a second design center in India and gains an additional 80 engineers. "The focus of the Ranchi office will be to provide lower-cost offshore design center services for our customer's designs targeting 7- and 10-nm process technology," said Satish Bag... » read more

What Is Portable Stimulus?

By Brian Bailey - 23 Mar, 2017 - Comments: 0

When [getentity id="22028" e_name="Accellera"] first formed the [getentity id="22863" comment="Portable Stimulus Working Group”] and gave it that name, I was highly concerned. I expressed my frustration that the name, while fitting with what most people thought [getkc id="10" kc_name="verification"] is about, does not reflect the true nature of the standard being worked on. In short, it is no... » read more

Users Talk Back On Standards Process

By Brian Bailey - 23 Mar, 2017 - Comments: 0

One of the major themes of DVCon this year was the standard that currently goes by the name of Portable Stimulus (see related story, Portable Stimulus – The Name Must Change). It is not ready for prime time yet, but there was plenty to hear and learn about the emerging standard, including what users think about it and the standardization process. The panel gave the users the opportunity to vo... » read more

2017: Tool And Methodology Shifts

By Brian Bailey - 26 Jan, 2017 - Comments: 0

As the markets for semiconductor products evolve, so do the tools that enable automation, optimization and verification. While tools rarely go away, they do bend like plants toward light. Today, it is no longer the mobile phone industry that is defining the direction, but automotive and the Internet of Things (IoT). Both of these markets have very different requirements and each creates their o... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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