tag: Valtrix Systems

Chip Industry Week In Review
By The SE Staff - 26 Jul, 2024 - Comments: 0

The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Why RISC-V Is Succeeding
By Brian Bailey - 24 Feb, 2022 - Comments: 5

There is no disputing the excitement surround the introduction of the RISC-V processor architecture. Yet while many have called it a harbinger of a much broader open-source hardware movement, the reasons behind its success are not obvious, and the implications for an expansion of more open-source cores is far from certain. “The adoption of RISC-V as the preferred architecture for many sili... » read more

Domain-Specific Design Drives EDA Changes
By Ann Mutschler - 03 Jan, 2022 - Comments: 0

The chip design ecosystem is beginning to pivot toward domain-specific architectures, setting off a scramble among tools vendors to simplify and optimize existing tools and methodologies. The move reflects a sharp slowdown in Moore's Law scaling as the best approach for improving performance and reducing power. In its place, chipmakers — which now includes systems companies — are pushing... » read more

Debugging Embedded Applications
By Ann Mutschler - 10 Nov, 2021 - Comments: 0

Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation ... » read more

Debug: The Schedule Killer
By Brian Bailey - 30 Jun, 2021 - Comments: 0

Debug often has been labeled the curse of management and schedules. It is considered unpredictable and often can happen close to the end of the development cycle, or even after – leading to frantic attempts at work-arounds. And the problem is growing. "Historically, about 40% of time is spent in debug, and that aspect is becoming more complex," says Vijay Chobisa, director of product manag... » read more

Merging Verification And Test
By Brian Bailey - 22 Apr, 2021 - Comments: 0

While the disciplines of functional verification and test serve different purposes, their histories were once closely intertwined. Recent safety and security monitoring requirements coupled with capabilities being embedded into devices is bringing them closer together again, but can they successfully cooperate to bring about improvements in both? Getting there may be difficult. Three phases ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 26 Mar, 2021 - Comments: 0

Companies Pearl Semiconductor launched to provide low and ultra-low noise timing products. “Pearl is a timing company developing resonator-agnostic solutions. We work with quartz crystals, MEMS resonators or whatever achieves superior performance,” said Ayman Ahmed, CEO of Pearl Semiconductor. “Current and future automotive applications demand low noise and a wide operating temperatur... » read more

Demand for IC Resilience Drives Methodology Changes
By Ann Mutschler - 25 Mar, 2021 - Comments: 0

Applications that demand safety, security, and resilience are driving new ways of thinking about design, verification, and the long-term reliability of chips on a mass scale. The need is growing for chips that can process more data faster, over longer periods of time, and often within a shrinking power budget. That, in turn, is forcing changes at multiple levels, at the architecture, design,... » read more

When Is Verification Done?
By Ann Mutschler - 25 Feb, 2021 - Comments: 0

Even with the billions of dollars spent on R&D for EDA tools, and tens of billions more on verification labor, only 30% to 50% of ASIC designs are first time right, according to Wilson Research Group and Siemens EDA. Even then, these designs still have bugs. They’re just not catastrophic enough to cause a re-spin. This means more efficient verification is needed. Until then, verificati... » read more

RISC-V Verification Challenges Spread
By Ann Mutschler - 22 Dec, 2020 - Comments: 0

The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies. The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor... » read more

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