中文 English

Week In Review: Design, Low Power

ML for DFM pattern analysis; low noise timing; OmniXtend working group; Flex Logix funding.

popularity

Companies
Pearl Semiconductor launched to provide low and ultra-low noise timing products. “Pearl is a timing company developing resonator-agnostic solutions. We work with quartz crystals, MEMS resonators or whatever achieves superior performance,” said Ayman Ahmed, CEO of Pearl Semiconductor.

“Current and future automotive applications demand low noise and a wide operating temperature range,” added Mostafa Elkhouly, vice president of marketing & business development, Pearl Semiconductor. “Our low-noise single-die MEMS SAW-based products achieve a typical performance of 350 femtoseconds for integrated phase jitter with an operating temperature range up to +125 oC, making them ideal candidates for automotive.” A spin out from Si-Ware Systems, a provider of spectral sensors and handheld spectral scanners, Pearl Semiconductor is headquartered in Amsterdam, The Netherlands, with main R&D in Cairo, Egypt.

Flex Logix raised $55.0 million in a Series D funding round. The round was led by Mithril Capital Management with participation by existing investors Lux Capital, Eclipse Ventures, and the Tate Family Trust. “We are impressed with the very high inference-throughput/$ architecture that Flex Logix has developed based on unique intellectual property that gives it a sustainable competitive advantage in a very high growth market,” said Ajay Royan, managing general partner and founder of Mithril Capital Management. The funding “will allow us to further build out our software, engineering and customer support teams and accelerate the availability of our hardware and software for edge enterprise applications,” said Flex Logix CEO Geoff Tate, adding that InferX XI accelerator chips and boards along with a compiler will be available mid-2021.

Collaboration
Cadence and GlobalFoundries are collaborating on design for manufacturing signoff with machine learning prediction capabilities. Cadence’s Litho Physical Analyzer, a DFM pattern analysis tool integrated with GF-developed ML models, has been qualified for GF’s 12LP and 12LP+ solutions. GF has released a corresponding ML-enhanced DFM kit as an update to its 12LP process design kits (PDKs), with the 12LP+ version upcoming. The two companies also successfully taped out a Tensilica test chip on GF’s 22FDX platform. This design used the Cadence digital full flow with Adaptive Body Bias (ABB) foundation IP along with the Cadence Tensilica HiFi 5 and Fusion F1 DSPs.

Global Unichip Corporation (GUC) adopted Ansys’ HFSS 3D Layout’s advanced simulation workflow to speed IC design. GUC said the workflow helped it incorporate die-to-die solutions across CoWoS, InFO, and interposer designs, including the newly announced GUC multi-die interLink (GLink) interface for developing leading-edge AI, HPC, and data center networking applications.

Keysight and Synopsys are teaming up to integrate Keysight’s RFPro solution with Synopsys’ Custom Compiler solution, enabling mutual customers to create 5G SoC designs. The integration adds electromagnetic (EM) analysis to the full-custom design flow based on the Synopsys Custom Design Platform and has been deployed at CoreHW, a developer of RF ICs.

Valtrix Systems and Codasip are working together on verification of RISC-V-based systems. Codasip is using Valtrix’s STING product in addition to Codasip Studio, in-house tools, and third-party tools for processor verification, citing the ability to generate portable self-checking stimulus across multiple device-under-test environments and to exercise architectural and micro-architectural features using its test stimulus programming framework.

Memory
Infineon Technologies launched its second-generation non-volatile Static RAMs (nvSRAM). They are qualified for QML-Q and high-reliability industrial specifications for harsh environments, including aerospace, industrial furnace, and railroad control applications. Under normal operating conditions, nvSRAM acts similarly to a conventional asynchronous SRAM. In the event of a power failure, a nvSRAM automatically saves a copy of the SRAM data into non-volatile memory. Both 5 V and 3 V versions support boot code, data logging, and calibration data storage.

Samsung Electronics uncorked a 512GB DDR5 module based on High-K Metal Gate (HKMG) process technology. By using HKMG material, Samsung says leakage will be reduced, improving performance. It should also use approximately 13% less power and is targeted at data centers.

Standards
CHIPS Alliance and RISC-V International will work jointly to update the OmniXtend Cache Coherency specification. The two groups formed a new OmniXtend working group which will focus on creating an open, cache coherent, unified memory standard for multicore compute architectures. The group will update the OmniXtend specification and protocol, build out architectural simulation models and a reference RTL implementation, as well as create a verification workbench. “We plan to allow for a mixture of hardware IP blocks, giving developers more design flexibility so they can choose what works best for their specific application needs,” said Rob Mains, General Manager at CHIPS Alliance.

Events
Find a new conference or learning opportunity at our events page, or check out an upcoming webinar.

The U.S. government-focused electronics conference GOMACTech will be held Mar. 29-Apr. 1. The CHIPS Alliance Spring Workshop will take place March 30.



Leave a Reply


(Note: This name will be displayed publicly)