tag: Vayavya Labs

Service Revenue Growing With Chip Complexity
By Ann Mutschler - 04 Nov, 2019 - Comments: 0

Rising complexity, new markets, and a shortage of in-house expertise are beginning to rekindle demand for services for the first time in nearly a decade. The semiconductor industry has been racing to design chips for a variety of new and existing applications, but they are facing challenges on a number of fronts: Leading-edge chips require new architectures due to a sharp reduction in s... » read more

DAC 2018: System Design, Cloud And Machine Learning
By Frank Schirrmeister - 28 Jun, 2018 - Comments: 0

This marks the 10th DAC that I have covered as a blogger. At DAC 2008 in Anaheim, the industry had just come together behind the SystemC TLM 2.0 standard to enable virtual platforms, finally getting to model interoperability. System design is the common thread that is also present in this year’s DAC in 2018 in San Francisco. But a lot has changed. Big data analytics, artificial intelligence a... » read more

Open Standards For Verification?
By Ann Mutschler - 01 Jun, 2016 - Comments: 0

The increasing use of verification data for analyzing and testing complex designs is raising the stakes for more standardized or interoperable database formats. While interoperability between databases in chip design is not a new idea, it has a renewed sense of urgency. It takes more time and money to verify increasingly complex chips, and more of that data needs to be used earlier in the fl... » read more

Software-Driven Verification (Part 3)
By Brian Bailey - 10 Feb, 2015 - Comments: 0

[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Software-Driven Verification (Part 2)
By Brian Bailey - 05 Jan, 2015 - Comments: 0

[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Software-Driven Verification (Part 1)
By Brian Bailey - 18 Dec, 2014 - Comments: 1

[getkc id="10" comment="Functional Verification"] has been powered by tools that require hardware to look like the kinds of systems that were being designed two decades ago. Those limitations are putting chips at risk and a new approach to the problem is long overdue. Semiconductor Engineering sat down with Frank Schirrmeister, group director, product marketing for System Development Suite at [... » read more

Big Shift In SoC Verification
By Ed Sperling - 31 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

Big Shift In SoC Verification
By Ed Sperling - 17 Mar, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

Do We Need A “Glue” Engineer?
By Brian Fuller - 13 Mar, 2014 - Comments: 0

Design and verification are so complex today and fraught with market risk that it keeps managers awake and sweating at night. So much of design is carved up in IP blocks and subsystems, each with their own verification issues and methodologies. To manage the complexity the design is partitioned, and so too are the teams. But as software verification becomes more crucial to system-design succ... » read more

Big Shift In SoC Verification
By Ed Sperling - 06 Mar, 2014 - Comments: 5

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

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