Who Benefits From Chiplets, And When

By Ed Sperling - 31 May, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

Is AI Improving A Broken Process?

By Brian Bailey - 26 May, 2022 - Comments: 0

Verification is fundamentally comparing two models, each derived independently, to find out if there are any different behaviors expressed between the two models. One of those models represents the intended design, and the other is part of the testbench. In an ideal flow, the design model would be derived from the specification, and each stage of the design process would be adding other deta... » read more

RISC-V: Advanced Virtual Prototyping Solutions

By Technical Paper Link - 23 May, 2022 - Comments: 0

New technical paper titled "Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges" from researchers at Institute of Computer Science, University of Bremen and Cyber-Physical Systems, DFKI GmbH. Abstract "Virtual prototypes (VPs) are crucial in today’s design flow. VPs are predominantly created in SystemC transaction-level modelin... » read more

The Challenges Of Incremental Verification

By Brian Bailey - 28 Apr, 2022 - Comments: 1

Verification consumes more time and resources than design, and yet little headway is being made to optimize it. The reasons are complex, and there are more questions than there are answers. For example, what is the minimum verification required to gain confidence in a design change? How can you minimize the cost of finding out that the change was bad, or that it had unintended consequences? ... » read more

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality

By Philippe Luc - 28 Apr, 2022 - Comments: 0

I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the verification?” There is no easy answer. There are several common indicators used in the industry such as coverage and bug curve. While they are absolutely necessary, these are not enough to reach the ... » read more

Arm’s Input Qualification Methodology Using PowerPro

By Siemens EDA - 27 Apr, 2022 - Comments: 0

This white paper proposes a new automated input qualification methodology that Arm developed using Siemens EDA’s PowerPro software portfolio that performs various data integrity checks at the IC design build and prototype stage. This methodology ensures in quicker iterations that input data are high fidelity, leading to a well correlated power numbers. Should multiple iterations be necessary,... » read more

Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection

By Technical Paper Link - 19 Apr, 2022 - Comments: 0

Abstract "Globalization in the semiconductor industry enables fabless design houses to reduce their costs, save time, and make use of newer technologies. However, the offshoring of Integrated Circuit (IC) fabrication has negative sides, including threats such as Hardware Trojans (HTs) - a type of malicious logic that is not trivial to detect. One aspect of IC design that is not affected by g... » read more

Reliable DRC Voltage Text Annotation Means Faster And More Accurate DRC Verification

By Abdellah Bakhali - 14 Apr, 2022 - Comments: 0

As the potential for complex interactions between voltage domains grows significantly with the increase in design density at each new process node, the complexity of spacing checks in design rule checking (DRC) also increases. To minimize these types of risk, many simple spacing checks have evolved to become voltage-aware DRC (VA-DRC) checks that incorporate voltage values to determine the requ... » read more

Automated DRC Voltage Annotation Provides Faster And More Accurate Verification For Voltage-Aware Spacing Rules

By Siemens EDA - 13 Apr, 2022 - Comments: 0

Accurate and repeatable reliability verification is now essential for both advanced node designs and the increasingly complex products being produced at established nodes. To ensure compliance with all process, reliability, and power management requirements, voltage-aware DRC applies variable spacing requirements, based on either the absolute voltage or delta voltage values, to accurately evalu... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards

By Cadence - 13 Apr, 2022 - Comments: 0

By Martin James, Gary Dick, and Arif Khan, Cadence with Suhas Pai and Brian Rea, Intel The Compute Express Link™ (CXL™) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, ... » read more

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tag: verification

Who Benefits From Chiplets, And When

Is AI Improving A Broken Process?

RISC-V: Advanced Virtual Prototyping Solutions

The Challenges Of Incremental Verification

Measuring The Complexity Of Processor Bugs To Improve Testbench Quality

Arm’s Input Qualification Methodology Using PowerPro

Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection

Reliable DRC Voltage Text Annotation Means Faster And More Accurate DRC Verification

Automated DRC Voltage Annotation Provides Faster And More Accurate Verification For Voltage-Aware Spacing Rules

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards

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