tag: verification

Constraint-Based Verification Of Clock Domain Crossings
By Synopsys - 25 Mar, 2020 - Comments: 0

There are many measures of the ever-growing size and complexity of semiconductor devices: die area, transistor count, gate count, size of memories, amount of parallel processing and more. All these factors mean more time spent in design, but they also have a major impact on verification. Since virtually all industry studies show verification time and effort growing faster than design, this impa... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Mar, 2020 - Comments: 0

Ansys will acquire Lumerical, a developer of photonic design and simulation tools. "The potential of photonics in applications like 5G, IIoT and autonomous vehicles can only be realized by solving immense multiphysics device and system challenges," said James Pond, co-CEO and CTO of Lumerical. "Together, Lumerical and Ansys are uniquely positioned to provide the necessary solutions, and custome... » read more

A Complete System-Level Security Verification Methodology
By Cadence - 04 Mar, 2020 - Comments: 0

Hardware is at the root of all digital systems, and security must be considered during the system-on-chip (SoC) design and verification process. Verifying the security of an SoC design is challenging because of time to market pressure and resource constraints. Resources allocated to the already time-consuming task of functional verification must be diverted to security verification, which requi... » read more

Banking On FPGA Prototyping
By Ed Sperling - 04 Mar, 2020 - Comments: 0

Juergen Jaeger, product management director at Cadence, explains how FPGA prototyping can improve efficiency and reduce design costs, what the development costs are for various phases of the design flow, how that changes across different markets such as automotive and 5G, and why software is now the biggest knob to turn for reducing cost and time to market. » read more

Fusing Implementation And Verification
By Ed Sperling - 02 Mar, 2020 - Comments: 0

Susantha Wijesekara, senior application engineer at Synopsys, drills down into how to re-use Tcl scripts for static verification, what needs to be done with those scripts to make that possible, why that is critical to “shift left,” and how that approach saves time, money, and improves quality. » read more

A New Breed Of Engineer
By Brian Bailey - 27 Feb, 2020 - Comments: 6

The industry loves to move in straight lines. Each generation of silicon is more-or-less a linear extrapolation of what came before. There are many reasons for this – products continue to evolve within the industry, adding new or higher performance interfaces, risk levels are lower when the minimum amount is changed for any chip spin, existing software is more likely to run with only minor mo... » read more

Simulation: Go Parallel Or Go Home
By Taruna Reddy - 27 Feb, 2020 - Comments: 0

Although complemented by other valuable technologies, functional simulation remains at the heart of semiconductor verification. Every chip project still develops a testbench, usually compliant with the Universal Verification Methodology (UVM), and a large test suite. Constrained-random stimulus generation has largely replaced hand-crafted tests, but at the expense of much more simulation time. ... » read more

Why Is PSS So Important?
By Ed Sperling - 25 Feb, 2020 - Comments: 0

Robert Hoogenstryd, product marketing manager at Mentor, a Siemens Business, talks about the new testbench verification language standard, what are the big advantages of using PSS, what kinds of challenges this language solves, and how much time this approach can save. » read more

Earlier Is Better In Latch-Up Detection
By Flint Yoder - 13 Feb, 2020 - Comments: 1

Physical verification is an essential step in integrated circuit (IC) design verification. Foundries provide design rule manuals that specify the precise physical requirements needed to ensure the design can be correctly manufactured, and the verification team runs the layout through checks based on those rules to ensure compliance. However, ensuring that a design can be manufactured does not g... » read more

Reducing Power At RTL
By Ann Mutschler - 13 Feb, 2020 - Comments: 0

Power management and reduction at the register transfer level is becoming more problematic as more heterogeneous elements are added into advanced designs and more components are dependent on interactions with other components. This has been a growing problem in leading-edge designs for the past couple of process nodes, but similar issues have begun creeping into less-sophisticated designs as... » read more

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