tag: verification

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL
By Vlada Kalinic - 08 Jan, 2026 - Comments: 0

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this code to RTL, which can be input to the traditional RTL downstream flow (RTL/GDS). Formally checking generated RTL can be difficult to analyze, as errors cannot be correlated to the HLS source code. ... » read more

Chip Industry’s Top Videos 2025
By The SE Staff - 30 Dec, 2025 - Comments: 0

Rising complexity, new architectures, and AI's permeation of nearly everything left engineers struggling to keep up in 2025, as evidenced by this year's viewership numbers. Among the hottest topics were verification, agentic AI, DRAM/HBM, optimization of data movement, chiplets, and heterogeneous integration, but there was steady traffic growth across all sectors. Top 10 most-watched videos ... » read more

Software-Defined Hardware-Assisted Verification: Scaling To Quadrillions Of Cycles For Verification In The AI Era
By Frank Schirrmeister - 23 Dec, 2025 - Comments: 0

The semiconductor industry is at an inflection point. The convergence of advanced multi-die architectures, AI-driven workloads, and rapidly evolving interface protocols is creating unprecedented design complexity. At the same time, market pressures demand faster time-to-market and higher performance, leaving little room for error. From data center to edge developments, users have to run softwar... » read more

Autonomous ASIC Root Cause Analysis
By Mehir Arora - 23 Dec, 2025 - Comments: 0

By Mehir Arora and Zackary Glazewski Over 50% of frontend ASIC hardware engineering time is spent on debugging and root cause analysis, spent churning through millions of lines of code and terabytes of waveform data. Despite this, there are no existing solutions for autonomous root cause analysis that use both code and waveform data. ChipAgents Root Cause Analysis (ChipAgents RCA) is the fir... » read more

2025 – A Year Of Change And Anticipation
By Brian Bailey - 23 Dec, 2025 - Comments: 0

2025 has certainly been a year of unexpected changes. These had a significant impact on the semiconductor industry and everything that supports it. Not all the changes have been bad, but flexibility has been a requirement for continued success or to make the most of an opportunity provided. Some industries, such as aerospace and defense, are seeing a significant boost around the world. Data ... » read more

Tracking Your Preferences
By Brian Bailey - 23 Dec, 2025 - Comments: 0

I like to use my last blog of the year to focus on you, the reader. You provide valuable feedback to me and the rest of the team at Semiconductor Engineering. What do you want to see us write about? How in-depth should things be? This is always a balance between the amount of information provided and the rate at which readers tire with an article. My focus is the channels I write for – Sys... » read more

AI In A/MS IC Design: Between Buzzword And Productivity Boost
By Benjamin Prautsch - 11 Dec, 2025 - Comments: 0

In the past few years, AI has burst onto the public stage in grand style. This ongoing trend is apparent in the rising number of AI applications in everyday life. But more and more, it can also be seen in a broad range of technical niches, where the main motivation is AI’s promise of continuously increasing efficiency. One such niche that has seen decades of attempts to achieve greater eff... » read more

Streamlining DO-254 Compliance: The Power Of Automated Clock-Domain Crossing Verification
By Kurt Takara - 11 Dec, 2025 - Comments: 0

In the realm of safety-critical electronic hardware, particularly those governed by DO-254 compliance directives, ensuring design integrity is paramount. One of the most insidious challenges designers face is clock-domain crossing (CDC) violations. When data moves between asynchronous clock domains, it can lead to metastability issues, causing unpredictable behavior, data loss or corruption, an... » read more

Arm Performance Cookbook: Your Guide to Optimal Design and Verification (EBook)
By Cadence - 10 Dec, 2025 - Comments: 0

The Performance Cookbook for Arm is your essential resource for mastering the complexities of system-level performance, architecture exploration, and SoC verification. Why Download the Performance Cookbook? In-Depth Exploration - Dive into the evolution of Arm compute subsystem architectures, with detailed coverage on how critical components interact to deliver optimal performance be... » read more

Calibre 3DPERC: Your Key To Robust ESD Solutions For 3D ICs
By Siemens EDA - 03 Dec, 2025 - Comments: 0

As semiconductor designs move beyond the limits of planar integration, three-dimensional (3D) IC technology introduces new challenges for ESD (electrostatic discharge) protection and verification. In this paper, author Dina Medhat explores how traditional verification methods must evolve for 3D ICs, detailing the crucial differences in pad classification, protection circuit strategies and the i... » read more

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