tag: verification

Boosting Analog Reliability
By Ed Sperling - 17 Jan, 2019 - Comments: 0

Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

Computer Vision Sees a Bright Future
By Mentor, a Siemens Business - 16 Jan, 2019 - Comments: 0

Computer vision is powering advances in automotive, medical, consumer, and agriculture markets. Because the world of computer vision coupled with machine learning evolves so quickly, teams need a way to design and verify an algorithm while the specifications and requirements evolve without starting over every time there is a change. The only way to successfully develop these systems is to use h... » read more

Testing AI Systems
By Ed Sperling - 15 Jan, 2019 - Comments: 0

AI is booming. It's coming to a device near you—maybe even inside of you. And AI will be used to design, manufacture and even ship those devices, regardless of what they are, where they are used, or how they are transported. The big questions now are whether these systems work, for how long—and what do those metrics even mean? An AI system, or AI-enhanced system, is supposed to adapt ove... » read more

Chip Industry In Rapid Transition
By Ed Sperling - 09 Jan, 2019 - Comments: 0

Wally Rhines, CEO Emeritus at Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about global economics, AI, the growing emphasis on customization, and the impact of security and higher abstraction levels. What follows are excerpts of that conversation. SE: Where do you see the biggest changes happening across the chip industry? Rhines: 2018 was a hot year for fab... » read more

Using Software Approaches In Hardware Verification
By Ann Mutschler - 26 Dec, 2018 - Comments: 1

Agile methodologies, created to improve quality in software code, increasingly are being applied to hardware verification. This is less of a drastic shift than it might first appear. Developing a verification testbench is largely software, and similar methodologies can be used for reducing bugs in hardware. “A testbench is nothing more than a big software project, and it makes perfect s... » read more

Fundamental Shifts In 2018
By Brian Bailey - 20 Dec, 2018 - Comments: 1

What surprised the industry in 2018?  While business has been strong, markets are changing, product categories are shifting and clouds are forming on the horizon. As 2018 comes to a close, most companies are pretty happy with the way everything turned out. Business has been booming, new product categories developing, and profits are meeting or beating market expectations. "2018 was indeed a... » read more

Verification Throughput Is Set To Increase By Leaps And Bounds In 2019
By Frank Schirrmeister - 20 Dec, 2018 - Comments: 0

In June 2015, I wrote the blog “Towards A Metric To Measure Verification Computing Efficiency” that introduced what we now refer to here at Cadence as the “productivity wheel” for verification payloads—the sequence of “build”, “allocate”, “run” and “debug” that is repeated thousands of times during a project. It was meant to set up the launch of the Palladium Z1 platfo... » read more

Debug Tops Verification Tasks
By Ann Mutschler - 20 Dec, 2018 - Comments: 0

Verification engineers are spending an increased percentage of their time in debug — 44%, according to a recent survey by the Wilson Research Group. There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are be... » read more

What Makes A Chip Design Successful Today?
By Brian Bailey - 13 Dec, 2018 - Comments: 0

"Transistors are free" was the rallying cry of the semiconductor industry during the 1990s and early 2000s. That is no longer true. The end of Dennard scaling made the simultaneous use of all the transistors troublesome, but transistors remained effectively unlimited. This led to an era where large amounts of flexibility could be built into a chip. It didn't matter if all of it was being use... » read more

Efficient Low Power Verification & Debug Methodology Using Power-Aware Simulation
By Himanshu Bhatt - 13 Dec, 2018 - Comments: 1

By Himanshu Bhatt and Shreedhar Ramachandra Isolation, retention, and power switches are some of the important functionalities of power-aware designs that use some of the common low power techniques (e.g.) power shutoff, multi-voltage and advanced techniques (e.g.) DVFS, Low VDD standby, and biasing. The strategies for isolation, retention, and level shifter are specified in the power forma... » read more

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