tag: verification

Can AI, 5G Chips Be Verified?
By Ed Sperling - 31 Jan, 2019 - Comments: 0

AI and 5G bode well for the semiconductor industry. They will require many billions of new, semi-customized and highly complex chips from the edge all the way to the data center, and they will require massive amounts of engineering time and tooling. But these technologies also are raising lots of questions on the design and verification front about what else can be automated and how to do it. ... » read more

Will Top-Down Hardware/Software Co-Design Ever Happen?
By Frank Schirrmeister - 31 Jan, 2019 - Comments: 0

Hardware/software co-design has been talked about, and predicted to be a problem, for at least two decades now. Why has the hardware/software development world not come to an end? In 1999, Wilf Corrigan—LSI Logic’s CEO at the time—said that the most pressing need for new EDA tools was a better methodology that would “allow software developers to begin software verification more near the... » read more

Pushing AI Into The Mainstream
By Brian Bailey - 31 Jan, 2019 - Comments: 0

Artificial intelligence is emerging as the driving force behind many advancements in technology, even though the industry has merely scratched the surface of what may be possible. But how deeply AI penetrates different market segments and technologies, and how quickly it pushes into the mainstream, depend on a variety of issues that still must be resolved. In addition to a plethora of techni... » read more

Connectivity Checking Is A Perfect Fit For Formal Verification
By Tom Anderson - 31 Jan, 2019 - Comments: 0

Formal verification has traditionally been regarded as an advanced technique for experts to thoroughly verify individual blocks of logic, or perhaps small clusters of blocks. However, if you talk to anyone involved in the field these days, you’ll find that the majority of formal users are running applications (“apps”) targeted for specific verification problems. Further, many of these app... » read more

Verifying AI Designs Thoroughly And Quickly
By Jean-Marie Brunet - 31 Jan, 2019 - Comments: 0

You can’t turn around these days without seeing a reference to AI – even as a consumer. AI, or artificial intelligence, is hot due to the new machine-learning (ML) techniques that are evolving daily. It’s often cited as one of the critical markets for electronics purveyors, but it’s not really a market: it’s a technology. And it’s quietly – or not so quietly – moving into many, ... » read more

A Simplified Way to Debug IIP Designs and SoC
By Synopsys - 30 Jan, 2019 - Comments: 0

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. It's not uncommon for an engineer to run the verification test on what appears to be the main design problem, only to find the problem in the dump. Traditional debug techniques don't always help to localize the issue. This whitepaper... » read more

Taming Concurrency
By Brian Bailey - 17 Jan, 2019 - Comments: 2

Concurrency adds complexity for which the industry lacks appropriate tools, and the problem has grown to the point where errors can creep into designs with no easy or consistent way to detect them. In the past, when chips were essentially a single pipeline, this wasn't a problem. In fact, the early pioneers of EDA created a suitable language to describe and contain the necessary concurrency ... » read more

Efficient Hierarchical Verification For Low Power Designs
By Susantha Wijesekara - 17 Jan, 2019 - Comments: 0

By Susantha Wijesekara and Himanshu Bhatt Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, designers use a black box, liberty model based hierarchical flow, timing model (ETM) flow or stub/glass box flows that offer various degrees of trade-offs for... » read more

Boosting Analog Reliability
By Ed Sperling - 17 Jan, 2019 - Comments: 0

Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

Computer Vision Sees a Bright Future
By Mentor, a Siemens Business - 16 Jan, 2019 - Comments: 0

Computer vision is powering advances in automotive, medical, consumer, and agriculture markets. Because the world of computer vision coupled with machine learning evolves so quickly, teams need a way to design and verify an algorithm while the specifications and requirements evolve without starting over every time there is a change. The only way to successfully develop these systems is to use h... » read more

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