tag: verification

Using Formal Verification To Prevent Catastrophic Security Breaches
By Dave Kelf - 29 Sep, 2016 - Comments: 0

The news of last week’s Yahoo hack that affected 500-million or so users sent shock waves of anxiety far and wide. It’s not clear yet how the massive data breach occurred or through what means the hackers accessed the network. It could be the chips that drive the network, often vulnerable to attacks on their operational integrity. It’s no surprise, then, that semiconductor companies ar... » read more

Rethinking Verification For Cars
By Ann Mutschler - 29 Sep, 2016 - Comments: 0

As the amount of electronic content in a car increases, so does the number of questions about how to improve reliability of those systems. Unlike an [getkc id="76" kc_name="IoT"] device, which is expected last a couple of years, automotive electronics fall into a class of safety-critical devices. There are standards for verifying these devices, new test methodologies, and there is far mo... » read more

Gaps In The Verification Flow
By Brian Bailey - 29 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

The 2016 Wilson Research Group Functional Verification Study
By Harry Foster - 08 Sep, 2016 - Comments: 0

I am writing a series of blogs that presents the findings from our new 2016 Wilson Research Group Functional Verification Study. Similar to my previous 2014 Wilson Research Group functional verification study blogs, I plan to begin this set of blogs with an exclusive focus on FPGA trends. Why? For the following reasons: Some of the more interesting trends in our 2016 study are related to F... » read more

Managing Power Without Impacting Design Intent
By Christine Young - 08 Sep, 2016 - Comments: 0

The good news is that there are many techniques available to optimize power in your design. The not-so-good news? Many of these power management techniques also create new complexities in the physical and functional behavior of electronic designs. Fortunately, there’s more good news: implementing a power-aware verification methodology can help you verify power optimization without detracti... » read more

Power Options And Issues
By Ann Mutschler - 08 Sep, 2016 - Comments: 0

In the quest to get SoC power right as early as possible in the design flow, it still holds true that the biggest impact occurs at the beginning of the project, with diminished results as a design progresses through the flow toward tapeout. [getentity id="22186" e_name="ARM's"] big.LITTLE architecture has gained a lot of traction here, prompting MediaTek to introduce its Tri-Gear big.Medium.... » read more

Tech Talk: Power Signoff
By Ed Sperling - 08 Sep, 2016 - Comments: 0

Ansys' Aveek Sarkar the challenges of power signoff at advanced process nodes, the impact of over-design, and what's necessary for sufficient coverage. [youtube vid=VQoT2KYW-AM] » read more

The Future of UVM
By Neil Johnson - 26 Aug, 2016 - Comments: 7

It’s time for a frank discussion on the future of [gettech id="31055" comment="UVM"]. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to use UVM the right thing to do? Do we have hard evidence that supports our continued usage of UVM? Do we actually benefit from it or do we just think we benefit? ... » read more

Customizable Apps – Avoiding The Pitfalls Of EDA Frameworks
By Dave Kelf - 25 Aug, 2016 - Comments: 0

For those of us involved with EDA tools in the late '80s and early '90s, the word “frameworks” brings back memories of rigid methodology and use models, coupled with CAD complexity. Cadence and Mentor, among others, proposed the EDA framework as a mechanism to provide design revision management coupled with tool flow control (I can already imagine your eyes glazing over). For some situat... » read more

FPGA Prototyping Gains Ground
By Jeff Dorsch - 25 Aug, 2016 - Comments: 0

FPGA technology for design prototypes is making new inroads as demands increase for better integration between hardware and software. [gettech id="31071" comment="FPGA"] prototyping, also known as physical prototyping, has been supported by all of the major EDA players for some time, and it has been considered an essential tool for the largest chipmakers, along with emulation and simulation.... » read more

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