tag: verification

Optimizing Testbench Acceleration Performance
By Mentor, a Siemens Business - 10 Aug, 2016 - Comments: 0

Part 3 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three papers, architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performan... » read more

Connected Reliability Concerns
By Ed Sperling - 04 Aug, 2016 - Comments: 0

Ever since the invention of the integrated circuit, the focus has been on improving technology—making it faster, smaller, cheaper, while also cutting the power budget. With the advent of the IoT and ubiquitous connectivity, the value proposition will change. Rather than just improving the chip, the focus will shift to how that chip behaves in context. How does it work in a connected world... » read more

The Higher Cost Of Automotive
By Ann Mutschler - 04 Aug, 2016 - Comments: 0

A revolution is occurring under the hoods of vehicles today, as the automotive industry continues to add sophistication via electronics to vehicles at a pace never seen before. But because of the automotive ecosystem’s tiered structure, system companies, IP and embedded software developers and tools vendors must invest more just to participate. Robert Bates, chief safety officer in [getent... » read more

Mixed-signal/Low-power Design
By Jeff Dorsch - 03 Aug, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Formal Has Its Day
By Dave Kelf - 28 Jul, 2016 - Comments: 0

As new technologies receive more mainstream attention, it is common for the experts in the area to provide a critical mass of enthusiasm. Formal is in this mode with multiple meetings throughout the year and around the globe. Perhaps one of the most successful of these is the annual Formal Day event put on by Test & Verification Solutions (TVS) based in the UK. This live and online event is... » read more

Making Verification Easier
By Ann Mutschler - 28 Jul, 2016 - Comments: 0

SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

What’s Next For UVM?
By Brian Bailey - 28 Jul, 2016 - Comments: 0

The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

Mixed-signal/Low-power Design
By Jeff Dorsch - 26 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss mixed-signal/low-power IC design with Phil Matthews, director of engineering at Silicon Labs; Yanning Lu, director of analog IC design at Ambiq Micro; Krishna Balachandran, director of low power solutions marketing at [getentity id="22032" comment="Cadence"]; Geoffrey Ying, director of product marketing, AMS Group, [getentity id="22035" e_name="Syno... » read more

Introduction To Multi-Patterning
By Mentor, a Siemens Business - 20 Jul, 2016 - Comments: 0

Multi-patterning enables accurate lithographic resolution at today's most advanced nodes. Learn about the basics of this technology, and how it impacts your IC design and verification tasks and responsibilities. To read more, click here. » read more

Can Verification Meet In The Middle?
By Brian Bailey - 20 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss these issues with; Stan Sokorac, senior principal design engineer for [getentity id="22186" comment="ARM"]; Frank Schirrmeister, senior group director for product marketing for the system development suite of [getentity id="22032" e_name="Cadence"]; Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor Graphics"], Bernie... » read more

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