tag: verification

Verification Grows Up
By Brian Bailey - 05 Jan, 2016 - Comments: 2

Semiconductor Engineering sat down with a group of verification experts to see how much progress has been made in solving issues associated with the profession. Panelists included Mike Baird, President of Willamette HDL; Jin Zhang, VP marketing and customer relations for [getentity id="22147" comment="Oski Technology"] and Lauro Rizzatti, a marketing consultant and previously the general manage... » read more

What Goes Wrong With IP
By Ed Sperling - 31 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about the future of IP with Rob Aitken, R&D fellow at [getentity id="22186" comment="ARM"]; Mike Gianfagna, vice president of marketing at [getentity id="22242" e_name="eSilicon"]; Judd Heape, vice president of product applications at Apical; and Bernard Murphy, an independent industry consultant. What follows are excerpts of that discussion, which... » read more

Defining Sufficient Coverage
By Brian Bailey - 28 Dec, 2015 - Comments: 0

Semiconductor engineering sat down to discuss the definition of sufficiency of coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"]; Larry Vivolo was, at the time of this roundtable, senior director of product marketing for [get... » read more

Bridging Hardware And Software
By Ann Mutschler - 22 Dec, 2015 - Comments: 0

Since the advent of embedded systems there has been a struggle between hardware engineers trying to understand the mindset of their software counterparts, and vice versa. That struggle is alive and well today—and it's costing everyone money. This divide is rife with passion, territoriality and misunderstanding. It has delayed tapeouts, created errors and inefficiencies that take time and e... » read more

Verification Grows Up
By Brian Bailey - 22 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down with a group of verification experts to see how much progress has been made in solving issues associated with the profession. Panelists included Mike Baird, president of Willamette HDL; Jin Zhang, VP marketing and customer relations for [getentity id="22147" comment="Oski Technology"], and Lauro Rizzatti, a marketing consultant and previously the general manag... » read more

A History of (Premature) Optimization
By Neil Johnson - 22 Dec, 2015 - Comments: 0

I saw some material shared from DVCon Europe last month that suggested a competition brewing between shift left and agile in semiconductor development. As someone who’s been following shift left writing and been advocating for agile development, this kind of comparison is more than a little odd to see. It’s a comparison between two as yet amorphous development strategies, neither of which i... » read more

The Beginning
By Anupam Bakshi - 22 Dec, 2015 - Comments: 0

We all want our creations to transcend time. Our products, our designs—even our specifications. Specifications are more than just ideas or collections of requirements or static collections of implementation details. They live inside many chips and many designs, and the more flexible and portable they are, the longer they remain relevant. End devices may be replaced relatively quickly, but ... » read more

Outlook 2016 – The year of Horizontal and Vertical Flow Integration
By Frank Schirrmeister - 22 Dec, 2015 - Comments: 0

As 2015 comes to an end rapidly, the key question becomes what the next year will bring. Last year around this time, in my blog “The Next Big Shift In Verification”, I talked about software-driven verification as the next era of verification that follows the eras of directed testing and High-level Verification Language (HVL) driven verification. I also had referred to our System Development... » read more

U.V.M. Spells Relief
By Henry Chan - 22 Dec, 2015 - Comments: 0

Verification can be a challenging endeavor. As designs grow in size and complexity, engineers are having difficulty confirming their designs behave properly. This is where UVM may provide some relief. UVM aims to deliver an easier and more flexible way of creating robust test environments so that you can verify those difficult designs effortlessly. So what is UVM? UVM is a verification meth... » read more

Reflections On 2015
By Brian Bailey - 22 Dec, 2015 - Comments: 0

It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with SemiEngineering. We like to hold people's feet to the fire, but while the Pants-On-Fire meter may be applicable to politicians, we like to thin... » read more

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