System-Level Benefits Of The Versal Platform

By Xilinx - 01 Sep, 2021 - Comments: 0

Moore's Law has fueled the technological prosperity of the last 50 years, but it is generally believed now that Gordon Moore's 1965 forecast about the pace of innovation no longer holds true today. Continuing the silicon architectures of yesterday cannot meet the expanding demands of tomorrow's workloads. Frequently highlighted by today’s leaders in the field of computer architecture, to meet... » read more

ACAP At The Edge With The Versal AI Edge Series

By Xilinx - 30 Jun, 2021 - Comments: 0

This white paper introduces the AI Edge series to the Versal ACAP portfolio, a domain-specific architecture (DSA) that meets the strenuous demands of systems implemented in the 7nm silicon process. This series is optimized to meet the performance-per-watt requirements of edge nodes at or near the analog-digital boundary. Here, immediate response to the physical world is highly valued, and in ma... » read more

Synthetic Aperture And Plane Wave Ultrasound Imaging With Versal ACAP

By Xilinx - 06 Jan, 2021 - Comments: 0

Medical ultrasound is the most widely accepted and available form of diagnostic imaging today because of many significant advantages. It uses low-energy acoustic waves, and there are no known harmful side-effects on patients unlike potential ionizing radiation from X-rays or CT scans. Ultrasound can capture dynamic soft issue images, which X-rays cannot. Ultrasound systems are compact and trans... » read more

Versal Premium ACAPs: Breakthrough Integration of Networked IP On A Power-Optimized, Adaptable Platform

By Xilinx - 01 Dec, 2020 - Comments: 0

In every market across the world, continuous demand for higher bandwidth metro and core networks scales beyond what today's technologies can support. Data center-centric scientific, enterprise, and consumer applications demand more efficient, higher performance compute that scales beyond what traditional technologies can match. Discrete solutions cannot meet performance, thermal, and bandwidth ... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Versal ACAP

System-Level Benefits Of The Versal Platform

ACAP At The Edge With The Versal AI Edge Series

Synthetic Aperture And Plane Wave Ultrasound Imaging With Versal ACAP

Versal Premium ACAPs: Breakthrough Integration of Networked IP On A Power-Optimized, Adaptable Platform