Overcoming Challenges In Next-Generation SRAM Cell Architectures

By Benjamin Vincent - 18 Mar, 2021 - Comments: 0

Static Random-Access Memory (SRAM) has been a key element for logic circuitry since the early age of the semiconductor industry. The SRAM cell usually consists of six transistors connected to each other in order to perform logic storage and other functions. The size of the 6T (6 Transistors) SRAM cell has shrunk steadily over the past decades, thanks to Moore’s Law and the size reduction of t... » read more

SVT: Six Stacked Vertical Transistors

By Coventor - 17 Mar, 2021 - Comments: 0

This paper presents a new design architecture for advanced logic SRAM cells using six vertical transistors (with carrier transport along the Z direction), stacked one on top of each other. Virtual fabrication technology was used to identify different process integration schemes to enable the fabrication of this architecture with a competitive XY footprint at an advanced logic node: a unit cell ... » read more

The Impact of 3D Packaging

By Ann Mutschler - 11 Jun, 2009 - Comments: 0

With semiconductor packaging becoming a more crucial piece of the Moore’s Law roadmap, the industry is still sorting out the impact of a 3D design and packaging approach on design time, cost and power. 3D is now commonly used for high volume applications such as cell phones and SD cards, and is accomplished at the packaging step either through chip stacking or package-on-package (PoP) stac... » read more

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tag: vertical stacking

Overcoming Challenges In Next-Generation SRAM Cell Architectures

SVT: Six Stacked Vertical Transistors

The Impact of 3D Packaging