Is Verification At A Crossroads?

By Ann Mutschler - 27 Feb, 2014 - Comments: 1

As SoC verification methodologies and technologies have continued to mature, it’s an interesting time for engineering teams as they look to meet time to market goals and cut costs in an environment of cutthroat profit margins. Whether it is hardware emulation, FPGA prototyping, virtual prototyping or traditional software simulation, each platform has its strengths and drawbacks, with overl... » read more

Do Chips Really Work The First Time?

By Brian Bailey - 13 Feb, 2014 - Comments: 3

The industry used to have survey data that showed the number of respins required for a broad swath of designs and the principle causes of those respins. That was a good indicator of where tools or processes needed to be improved. At the time, the data showed that the primary cause of respins was functional errors, and since then EDA vendors have been beefing up tools in that area. Most of th... » read more

Powerful Software Optimization

By Brian Bailey - 05 Dec, 2013 - Comments: 0

It is commonly accepted that the higher you go in the design chain, the bigger the impact that design and implementation decision can have. While power optimization may have started deep in the silicon, the success of a product, such a smart phone, often is based on the time between charges. Batteries provide a finite energy resource, and while low-level optimization may focus on power reductio... » read more

Vista Virtual Prototyping

By Various Writers - 24 Oct, 2013 - Comments: 0

Vista Virtual Prototyping provides an early, abstract functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor models at speeds par with board support packages, providing sufficiently fast simulation models for OS and application software validation. The Vista Virtual Prototyping solution has two dist... » read more

The Week In Review: Oct. 4

By Mark LaPedus - 04 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling eSilicon introduced an automated multi-project wafer quote system, which allows companies to sort through a number of options and get pricing. The quotes are tied into TSMC's 20nm to 350nm processes, and GlobalFoundries’ 20nm to 180nm processes. The approach eliminates the need for companies to buy a full wafer if their volume requirements don’t warrant it... » read more

What Type of Insurance Do You Have?

By Tom De Schutter - 25 Sep, 2013 - Comments: 0

With the software development effort now accounting for roughly half of the overall SoC development cost, any delay on the software availability side can have a big impact on the SoC availability. As one engineer of a major semiconductor vendor expressed to me: “The SoC hardware is typically only available a couple of weeks before we want to announce and demonstrate it at a major show like CE... » read more

Experts At The Table: Next-Generation IP Landscape

By Ann Mutschler - 13 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss predictions about the next generation design IP landscape with Robert Aitken, R&D fellow at ARM; Laurent Moll, chief technical officer at Arteris; Susan Peterson, group director, product marketing for verification IP & memory models in the system & software realization group at Cadence; and John Koeter, vice preside... » read more

Simple Concepts Can Lead To Big Improvements

By Tom De Schutter - 22 Aug, 2013 - Comments: 0

By Tom De Schutter As I am just back from vacation, it is an ideal time to reflect on where we are with virtual prototyping and VDKs (Virtualizer Development Kits). For more than a year now we have been developing reference VDKs based on ARM’s Versatile Express board, and it has really made a difference in how we engage with customers. Although we always had demos, which were similar to t... » read more

Drafting For First Place

By Tom De Schutter - 25 Jul, 2013 - Comments: 0

By Tom De Schutter I am a big fan of professional cycling events, and nothing can beat the Tour de France. Every year the best riders from around the world gather for what looks like an impossible task: This year they have to ride 3,404 kilometers (2,115 miles) in three weeks including five hill stages and six mountain stages. After completing that entire distance, all that separates the first... » read more

Experts At The Table: SoC Prototyping

By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler System-Level Design sat down to discuss SoC prototyping with Hillel Miller, pre-silicon verification/emulation manager at Freescale Semiconductor; Frank Schirrmeister, group director, product marketing, for the system development suite at Cadence; and Mick Posner, director of product marketing at Synopsys. What follows are excerpts of that conversation. SLD: How... » read more

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Knowledge Centers
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NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

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What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

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Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

tag: virtual prototyping