RISC-V decoupled Vector Processing Unit (VPU) For HPC

A technical paper titled "Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications" was published by researchers at Barcelona Supercomputing Center, Spain. "The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of ... » read more

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches

New academic paper titled "Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution", from researchers at Univ. Grenoble Alpes, CEA-LIST. Abstract "This article presents Computational SRAM (C-SRAM) solution combining In- and Near-Memory Computing approaches. It allows performing arithmetic, logic, and co... » read more

Teaching Computers To See

Vision processing is emerging as a foundation technology for a number of high-growth applications, spurring a wave of intensive research to reduce power, improve performance, and push embedded vision into the mainstream to leverage economies of scale. What began as a relatively modest development effort has turned into an all-out race for a piece of this market, and for good reason. Mark... » read more