tag: VSoC

13000 FPS Vision System-on-Chip With Mixed-Signal Compressed Sensing
By Fraunhofer IIS/EAS - 09 Feb, 2022 - Comments: 0

This paper presents a monolithic high-speed VSoC (Vision-System-on-Chip) with three software-programmable 16-bit ASIPs (application-specific instruction-set processors), a 1024-fold column-parallel data path of charge-based convolution functionality, freely configurable A/D conversion, 8-bit processor elements with 128 bytes of RAM each, and asynchronously compressing output of sparse column da... » read more

Low-Latency Image Acquisition And Processing With A Programmable Vision-System-On-Chip
By Fraunhofer IIS/EAS - 12 Sep, 2018 - Comments: 0

This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction- set processors (ASIPs), image data within multiple regions of interest can be analyzed... » read more

A High-Speed Asynchronous Multi-Input Pipeline For Compaction And Transfer of Parallel SIMD Data
By Fraunhofer IIS/EAS - 16 Jul, 2018 - Comments: 0

Image sensors with programmable, highly parallel signal processing, so called Vision-Systems-on-Chip, perform computationally intensive tasks directly on the sensor itself. Therefore it is possible to limit the amount of output data to relevant image features only. Reading out such features presents a major challenge, since the position and number of features often is not known. Conventional sy... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy