Issues and solutions for developing vision-systems-on-chip.
Image sensors with programmable, highly parallel signal processing, so called Vision-Systems-on-Chip, perform computationally intensive tasks directly on the sensor itself. Therefore it is possible to limit the amount of output data to relevant image features only. Reading out such features presents a major challenge, since the position and number of features often is not known. Conventional synchronous buses as well as special event-based readout paths are unsuitable for such a system, since both continuous data, e.g. complete images, and sparse data, like feature coordinates, have to be transfered. A readout path based on an asynchronous pipeline is presented, which supports both readout modes with high speed. Furthermore, a method is introduced that, by serialization, allows for arbitrary data word widths without storing any control information within the data stream. The developed circuit components were measured on a proof-of-concept test chip in a 180 nm CMOS technology and were compared with implementations of asynchronous pipelines found in literature. In addition, the use of the pipeline in a Vision- System-on-Chip, which is still in production, is demonstrated.
To read more, click here.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Explosion of data is forcing significant changes in where processing is done.
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
2019 will be a year of change for the semiconductor industry as new fields drive technological advancements.
This new communications standard could transform architectural decisions across the industry, but not right away and not necessarily in obvious ways.
What hoops will designers have to jump through to avoid concurrency bugs?
Why managing power is becoming more difficult, more critical, and much more expensive.
Analog circuitry stopped following Moore’s Law a long time ago, but that hasn’t always helped.
Is it possible to reduce the power consumed by memory by 50%? Yes, but it requires work in the memory and at the architecture level.
Can mixed-signal architectures boost artificial intelligence performance using less power?
When going to a smaller node is no longer an option, how do you get better power performance? Several techniques are possible.
 |
 |
 |
 |
 |
 |
 |
 |
 |
 |
Leave a Reply