In-Product BTI Aging Sensor For Reliability Screening And Early Detection Of Material At Risk

We have developed a new reliability monitoring suite, within a proprietary IP block that we call a CV Core, with aging sensors embedded in the product layout and testable through the product I / O interface. We illustrate the application of the sensor suite with an example of the PMOS NBTI monitor, testable at the wafer level during product electrical wafer sort (EWS), as well after packaging a... » read more

Improving Chip Efficiency, Reliability, And Adaptability

Peter Schneider, director of Fraunhofer Institute for Integrated Circuits' Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about new models and approaches for ensuring the integrity and responsiveness of systems, and how this can be done within a given power budget and at various speeds. What follows are excerpts of that conversation. SE: Where are y... » read more

Testing The Stack: DFT Is Ready For 3D Devices

When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

Silicon Photonics: Automated Wafer-Level Probing And Silicon Photonics

As chip designers are pressed for ever-increasing data rates, the use of wavelength-division multiplexing (WDM) with infrared photonic signals as a data transfer medium is increasingly finding its way into CMOS silicon-based devices. Termed “silicon photonics” (SiPh), this technology is not only being used to displace traditional electrical interconnects, but also for a broad range of appli... » read more