Wafer-Scale CMOS-Integrated GFET Arrays With High Yield And Uniformity Designed For Biosensing Applications

A technical paper titled “Wafer-Scale Graphene Field-Effect Transistor Biosensor Arrays with Monolithic CMOS Readout” was published by researchers at VTT Technical Research Centre of Finland and Graphenea Semiconductor SLU. Abstract: "The reliability of analysis is becoming increasingly important as point-of-care diagnostics are transitioning from single-analyte detection toward multiplex... » read more

Full Wafer Integration of Aggressively Scaled 2D-Based Logic Circuits (Imec)

A technical paper titled "Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits" was published by researchers at Imec. "The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full waf... » read more

Scalable Approach to Fabricate Memristor Arrays at Wafer-scale

New technical paper titled "Wafer-scale solution-processed 2D material analog resistive memory array for memory-based computing" from researchers at National University of Singapore and Institute of High Performance Computing, Singapore. Abstract "Realization of high-density and reliable resistive random access memories based on two-dimensional semiconductors is crucial toward their develop... » read more