Full Wafer Integration of Aggressively Scaled 2D-Based Logic Circuits (Imec)


A technical paper titled “Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits” was published by researchers at Imec.

“The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full wafer integration of aggressively scaled 2D-based logic circuits, the status of developments, and the definition of the gaps to be bridged is provided. Today, typical test vehicles for 2D devices are single-sheet devices fully integrated in a lab environment, but transfer to a more scaled device in a fab environment has been demonstrated,” states the paper.

Find the technical paper here. Published September 2022.

Schram, T., Sutar, S., Radu, I., Asselberghs, I., Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits. Adv. Mater. 2022, 2109796. https://doi.org/10.1002/adma.202109796.

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